bindings/interrupt-controller/renesas%2Crza1-irqc.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,rza1-irqc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Chris Brandt <chris.brandt@renesas.com>
11   - Geert Uytterhoeven <geert+renesas@glider.be>
14   The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas RZ/A1 and
16     - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI interrupts,
17     - NMI edge select.
20   - $ref: /schemas/interrupt-controller.yaml#
25       - enum:
26           - renesas,r7s72100-irqc # RZ/A1H
27           - renesas,r7s9210-irqc  # RZ/A2M
28       - const: renesas,rza1-irqc
30   '#interrupt-cells':
33   '#address-cells':
36   interrupt-controller: true
41   interrupt-map:
45   interrupt-map-mask:
47       - const: 7
48       - const: 0
51   - compatible
52   - '#interrupt-cells'
53   - '#address-cells'
54   - interrupt-controller
55   - reg
56   - interrupt-map
57   - interrupt-map-mask
62   - |
63     #include <dt-bindings/interrupt-controller/arm-gic.h>
64     irqc: interrupt-controller@fcfef800 {
65             compatible = "renesas,r7s72100-irqc", "renesas,rza1-irqc";
66             #interrupt-cells = <2>;
67             #address-cells = <0>;
68             interrupt-controller;
70             interrupt-map =
79             interrupt-map-mask = <7 0>;