Lines Matching +full:level +full:- +full:detect
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/qcom,pdc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
14 Power Domain Controller (PDC) that is on always-on domain. In addition to
16 interrupt controller that can be used to help detect edge low interrupts as
17 well detect interrupts when the GIC is non-operational.
19 GIC is parent interrupt controller at the highest level. Platform interrupt
28 - enum:
29 - qcom,qdu1000-pdc
30 - qcom,sa8255p-pdc
31 - qcom,sa8775p-pdc
32 - qcom,sc7180-pdc
33 - qcom,sc7280-pdc
34 - qcom,sc8180x-pdc
35 - qcom,sc8280xp-pdc
36 - qcom,sdm670-pdc
37 - qcom,sdm845-pdc
38 - qcom,sdx55-pdc
39 - qcom,sdx65-pdc
40 - qcom,sdx75-pdc
41 - qcom,sm4450-pdc
42 - qcom,sm6350-pdc
43 - qcom,sm8150-pdc
44 - qcom,sm8250-pdc
45 - qcom,sm8350-pdc
46 - qcom,sm8450-pdc
47 - qcom,sm8550-pdc
48 - qcom,sm8650-pdc
49 - qcom,x1e80100-pdc
50 - const: qcom,pdc
55 - description: PDC base register region
56 - description: Edge or Level config register for SPI interrupts
58 '#interrupt-cells':
61 interrupt-controller: true
63 qcom,pdc-ranges:
64 $ref: /schemas/types.yaml#/definitions/uint32-matrix
69 - description: starting PDC port
70 - description: GIC hwirq number for the PDC port
71 - description: number of interrupts in sequence
78 - compatible
79 - reg
80 - '#interrupt-cells'
81 - interrupt-controller
82 - qcom,pdc-ranges
87 - |
88 #include <dt-bindings/interrupt-controller/irq.h>
90 pdc: interrupt-controller@b220000 {
91 compatible = "qcom,sdm845-pdc", "qcom,pdc";
93 qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
94 #interrupt-cells = <2>;
95 interrupt-parent = <&intc>;
96 interrupt-controller;
99 wake-device {
100 interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>;