bindings/interrupt-controller/qcom%2Cmpm.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/qcom,mpm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Shawn Guo <shawn.guo@linaro.org>
14   MSM Power Manager (MPM) that is in always-on domain. In addition to managing
21   - $ref: /schemas/interrupt-controller.yaml#
26       - const: qcom,mpm
34   qcom,rpm-msg-ram:
49   interrupt-controller: true
51   '#interrupt-cells':
54       The first cell is the MPM pin number for the interrupt, and the second
57   qcom,mpm-pin-count:
59       Specify the total MPM pin count that a SoC supports.
62   qcom,mpm-pin-map:
64       A set of MPM pin numbers and the corresponding GIC SPIs.
65     $ref: /schemas/types.yaml#/definitions/uint32-matrix
68         - description: MPM pin number
69         - description: GIC SPI number for the MPM pin
71   '#power-domain-cells':
75   - compatible
76   - interrupts
77   - mboxes
78   - interrupt-controller
79   - '#interrupt-cells'
80   - qcom,mpm-pin-count
81   - qcom,mpm-pin-map
82   - qcom,rpm-msg-ram
87   - |
88     #include <dt-bindings/interrupt-controller/arm-gic.h>
90     remoteproc-rpm {
91         compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc";
93         glink-edge {
94             compatible = "qcom,glink-rpm";
97             qcom,rpm-msg-ram = <&rpm_msg_ram>;
101         mpm: interrupt-controller {
103             qcom,rpm-msg-ram = <&apss_mpm>;
106             interrupt-controller;
107             #interrupt-cells = <2>;
108             interrupt-parent = <&intc>;
109             qcom,mpm-pin-count = <96>;
110             qcom,mpm-pin-map = <2 275>,
116             #power-domain-cells = <0>;