bindings/interrupt-controller/marvell%2Cmpic.yaml

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/marvell,mpic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Armada 370, 375, 38x, 39x, XP Interrupt Controller
10   - Marek Behún <kabel@kernel.org>
13   The top-level interrupt controller on Marvell Armada 370 and XP. On these
14   platforms it also provides inter-processor interrupts.
16   On Marvell Armada 375, 38x and 39x this controller is wired under ARM GIC.
26       - description: main registers
27       - description: per-cpu registers
31       - description: |
32           Parent interrupt on platforms where MPIC is not the top-level
33           interrupt controller.
35   interrupt-controller: true
37   '#interrupt-cells':
40   msi-controller: true
43   - compatible
44   - reg
45   - interrupt-controller
46   - '#interrupt-cells'
47   - msi-controller
52   - |
53     #include <dt-bindings/interrupt-controller/arm-gic.h>
54     #include <dt-bindings/interrupt-controller/irq.h>
56     interrupt-controller@20a00 {
60         interrupt-controller;
61         #interrupt-cells = <1>;
62         msi-controller;