Lines Matching +full:interrupt +full:- +full:controller
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM7120-style Level 2 and Broadcom BCM3380 Level 1 / Level 2
10 - Florian Fainelli <f.fainelli@gmail.com>
13 This interrupt controller hardware is a second level interrupt controller that
14 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
17 Such an interrupt controller has the following hardware design:
19 - outputs multiple interrupts signals towards its interrupt controller parent
21 - controls how some of the interrupts will be flowing, whether they will
22 directly output an interrupt signal towards the interrupt controller parent,
23 or if they will output an interrupt signal at this 2nd level interrupt
24 controller, in particular for UARTs
26 - has one 32-bit enable word and one 32-bit status word
28 - no atomic set/clear operations
30 - not all bits within the interrupt controller actually map to an interrupt
32 The typical hardware layout for this controller is represented below:
34 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
36 0 -----[ MUX ] ------------|==========> GIC interrupt 75
37 \-----------\
39 1 -----[ MUX ] --------)---|==========> GIC interrupt 76
40 \------------|
42 2 -----[ MUX ] --------)---|==========> GIC interrupt 77
43 \------------|
45 3 ---------------------|
46 4 ---------------------|
47 5 ---------------------|
48 7 ---------------------|---|===========> GIC interrupt 66
49 9 ---------------------|
50 10 --------------------|
51 11 --------------------/
53 6 ------------------------\
54 |===========> GIC interrupt 64
55 8 ------------------------/
62 The BCM3380 Level 1 / Level 2 interrupt controller shows up in various forms
65 - outputs a single interrupt signal to its interrupt controller parent
67 - contains one or more enable/status word pairs, which often appear at
70 - no atomic set/clear operations
73 - $ref: /schemas/interrupt-controller.yaml#
78 - enum:
79 - brcm,bcm7120-l2-intc
80 - brcm,bcm3380-l2-intc
88 interrupt-controller: true
90 "#interrupt-cells":
97 brcm,int-map-mask:
98 $ref: /schemas/types.yaml#/definitions/uint32-array
100 32-bits bit mask describing how many and which interrupts are wired to
101 this 2nd level interrupt controller, and how they match their respective
102 interrupt parents. Should match exactly the number of interrupts
105 brcm,irq-can-wake:
108 If present, this means the L2 controller can be used as a wakeup source
111 brcm,int-fwd-mask:
112 $ref: /schemas/types.yaml#/definitions/uint32-array
116 typically UARTs. Setting these bits will make their respective interrupt
117 outputs bypass this 2nd level interrupt controller completely; it is
118 completely transparent for the interrupt controller parent. This should
119 have one 32-bit word per enable/status pair.
124 - compatible
125 - reg
126 - interrupt-controller
127 - "#interrupt-cells"
128 - interrupts
131 - |
132 irq0_intc: interrupt-controller@f0406800 {
133 compatible = "brcm,bcm7120-l2-intc";
134 interrupt-parent = <&intc>;
135 #interrupt-cells = <1>;
137 interrupt-controller;
139 brcm,int-map-mask = <0xeb8>, <0x140>;
140 brcm,int-fwd-mask = <0x7>;
143 - |
144 irq1_intc: interrupt-controller@10000020 {
145 compatible = "brcm,bcm3380-l2-intc";
148 interrupt-controller;
149 #interrupt-cells = <1>;
150 interrupt-parent = <&cpu_intc>;