Lines Matching +full:cpu +full:- +full:interrupt +full:- +full:controller
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Generic Interrupt Controller v1 and v2
10 - Marc Zyngier <marc.zyngier@arm.com>
17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
18 Secondary GICs are cascaded into the upward interrupt controller and do not
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
29 - arm,arm11mp-gic
30 - arm,cortex-a15-gic
31 - arm,cortex-a7-gic
32 - arm,cortex-a5-gic
33 - arm,cortex-a9-gic
34 - arm,eb11mp-gic
35 - arm,gic-400
36 - arm,pl390
37 - arm,tc11mp-gic
38 - qcom,msm-8660-qgic
39 - qcom,msm-qgic2
41 - items:
42 - const: arm,gic-400
43 - enum:
44 - arm,cortex-a15-gic
45 - arm,cortex-a7-gic
47 - items:
48 - const: arm,arm1176jzf-devchip-gic
49 - const: arm,arm11mp-gic
51 - items:
52 - const: brcm,brahma-b15-gic
53 - const: arm,cortex-a15-gic
55 - oneOf:
56 - const: nvidia,tegra210-agic
57 - items:
58 - enum:
59 - nvidia,tegra186-agic
60 - nvidia,tegra194-agic
61 - nvidia,tegra234-agic
62 - const: nvidia,tegra210-agic
64 interrupt-controller: true
66 "#address-cells":
68 "#size-cells":
71 "#interrupt-cells":
74 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
77 The 2nd cell contains the interrupt number for the interrupt type.
78 SPI interrupts are in the range [0-987]. PPI interrupts are in the
79 range [0-15].
83 1 = low-to-high edge triggered
84 2 = high-to-low edge triggered (invalid for SPIs)
85 4 = active high level-sensitive
86 8 = active low level-sensitive (invalid for SPIs).
87 bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of
89 the interrupt is wired to that CPU. Only valid for PPI interrupts.
99 is the GIC cpu interface register base and size.
105 virtual cpu interface register base and size.
112 description: Interrupt source of the parent interrupt controller on
113 secondary GICs, or VGIC maintenance interrupt on primary GIC (see
117 cpu-offset:
118 description: per-cpu offset within the distributor and cpu interface
120 is cpu-offset * cpu-nr.
127 clock-names:
131 - const: ic_clk # for "arm,arm11mp-gic"
132 - const: PERIPHCLKEN # for "arm,cortex-a15-gic"
133 - items: # for "arm,cortex-a9-gic"
134 - const: PERIPHCLK
135 - const: PERIPHCLKEN
136 - const: clk # for "arm,gic-400" and "nvidia,tegra210"
137 - const: gclk # for "arm,pl390"
139 power-domains:
146 - compatible
147 - reg
150 "^v2m@[0-9a-f]+$":
153 * GICv2m extension for MSI/MSI-x support (Optional)
155 Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
156 This is enabled by specifying v2m sub-node(s).
160 const: arm,gic-v2m-frame
162 msi-controller: true
168 arm,msi-base-spi:
174 arm,msi-num-spis:
181 - compatible
182 - msi-controller
183 - reg
190 - |
192 intc: interrupt-controller@fff11000 {
193 compatible = "arm,cortex-a9-gic";
194 #interrupt-cells = <3>;
195 #address-cells = <1>;
196 interrupt-controller;
201 - |
203 interrupt-controller@2c001000 {
204 compatible = "arm,cortex-a15-gic";
205 #interrupt-cells = <3>;
206 interrupt-controller;
214 - |
215 // GICv2m extension for MSI/MSI-x support
216 interrupt-controller@e1101000 {
217 compatible = "arm,gic-400";
218 #interrupt-cells = <3>;
219 #address-cells = <1>;
220 #size-cells = <1>;
221 interrupt-controller;
230 compatible = "arm,gic-v2m-frame";
231 msi-controller;
238 compatible = "arm,gic-v2m-frame";
239 msi-controller;