iio/adc/st%2Cstm32-adc.yaml

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   STM32 ADC is a successive approximation analog-to-digital converter.
13   stored in a left-aligned or right-aligned 32-bit data register.
17   voltage goes beyond the user-defined, higher or lower thresholds.
22   - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
27       - st,stm32f4-adc-core
28       - st,stm32h7-adc-core
29       - st,stm32mp1-adc-core
30       - st,stm32mp13-adc-core
38         - stm32f4 and stm32h7 share a common ADC interrupt line.
39         - stm32mp1 has two separate interrupt lines, one for each ADC within
41         - stm32mp13 has an interrupt line per ADC block.
50         - "adc" clock: for the analog circuitry, common to all ADCs.
53         - "bus" clock: for registers access, common to all ADCs.
57   clock-names:
61   st,max-clk-rate-hz:
65   vdda-supply:
68   vref-supply:
71   booster-supply:
76   vdd-supply:
81   st,syscfg:
85     $ref: /schemas/types.yaml#/definitions/phandle-array
87   interrupt-controller: true
89   '#interrupt-cells':
92   '#address-cells':
95   '#size-cells':
98   access-controllers:
103   - if:
107             const: st,stm32f4-adc-core
114         clock-names:
119             - description: interrupt line common for all ADCs
121         st,max-clk-rate-hz:
126         booster-supply: false
128         vdd-supply: false
130         st,syscfg: false
132   - if:
136             const: st,stm32h7-adc-core
144         clock-names:
146             - const: bus
147             - const: adc
152             - description: interrupt line common for all ADCs
154         st,max-clk-rate-hz:
159         vdd-supply: false
161         st,syscfg: false
163   - if:
167             const: st,stm32mp1-adc-core
175         clock-names:
177             - const: bus
178             - const: adc
183             - description: interrupt line for ADC1
184             - description: interrupt line for ADC2
186         st,max-clk-rate-hz:
191   - if:
195             const: st,stm32mp13-adc-core
203         clock-names:
205             - const: bus
206             - const: adc
211             - description: ADC interrupt line
213         st,max-clk-rate-hz:
221   - compatible
222   - reg
223   - interrupts
224   - clocks
225   - clock-names
226   - vdda-supply
227   - vref-supply
228   - interrupt-controller
229   - '#interrupt-cells'
230   - '#address-cells'
231   - '#size-cells'
234   "^adc@[0-9]+$":
243           - st,stm32f4-adc
244           - st,stm32h7-adc
245           - st,stm32mp1-adc
246           - st,stm32mp13-adc
251             - 0x0:   ADC1
252             - 0x100: ADC2
253             - 0x200: ADC3 (stm32f4 only)
256       '#io-channel-cells':
259       '#address-cells':
262       '#size-cells':
267           IRQ Line for the ADC instance. Valid values are:
268             - 0 for adc@0 (single adc for stm32mp13)
269             - 1 for adc@100
270             - 2 for adc@200 (stm32f4 only)
283       dma-names:
286       assigned-resolution-bits:
289             - can be 6, 8, 10 or 12 on stm32f4 and stm32mp13
290             - can be 8, 10, 12, 14 or 16 on stm32h7 and stm32mp1
292       st,adc-channels:
294           List of single-ended channels muxed for this ADC. It can have up to:
295             - 16 channels, numbered from 0 to 15 (for in0..in15) on stm32f4
296             - 19 channels, numbered from 0 to 18 (for in0..in18) on stm32mp13.
297             - 20 channels, numbered from 0 to 19 (for in0..in19) on stm32h7 and
299         $ref: /schemas/types.yaml#/definitions/uint32-array
302       st,adc-diff-channels:
305           be configured as differential instead of single-ended on stm32h7 and
309           Note: At least one of "st,adc-channels" or "st,adc-diff-channels" is
313           used as single-ended and some other ones as differential (mixed). But
314           channels can't be configured both as single-ended and differential.
315         $ref: /schemas/types.yaml#/definitions/uint32-matrix
318             - description: |
322             - description: |
328       st,min-sample-time-nsecs:
333           array that matches "st,adc-channels" and/or "st,adc-diff-channels"
336         $ref: /schemas/types.yaml#/definitions/uint32-array
339       nvmem-cells:
341           - description: Phandle to the calibration vrefint data provided by otp
343       nvmem-cell-names:
345           - const: vrefint
348       "^channel@([0-9]|1[0-9])$":
365           diff-channels:
366             $ref: /schemas/types.yaml#/definitions/uint32-array
371           st,min-sample-time-ns:
378           - reg
383       - if:
387                 const: st,stm32f4-adc
393                 - 0x0
394                 - 0x100
395                 - 0x200
401             assigned-resolution-bits:
405             st,adc-channels:
412             st,adc-diff-channels: false
414             st,min-sample-time-nsecs:
421             - clocks
423       - if:
428                   - st,stm32h7-adc
429                   - st,stm32mp1-adc
435                 - 0x0
436                 - 0x100
442             assigned-resolution-bits:
446             st,adc-channels:
453             st,min-sample-time-nsecs:
460       - if:
464                 const: st,stm32mp13-adc
474             assigned-resolution-bits:
478             st,adc-channels:
485             st,min-sample-time-nsecs:
493       - compatible
494       - reg
495       - interrupts
496       - '#io-channel-cells'
499   - |
500     // Example 1: with stm32f429, ADC1, single-ended channel 8
502         compatible = "st,stm32f4-adc-core";
506         clock-names = "adc";
507         st,max-clk-rate-hz = <36000000>;
508         vdda-supply = <&vdda>;
509         vref-supply = <&vref>;
510         interrupt-controller;
511         #interrupt-cells = <1>;
512         #address-cells = <1>;
513         #size-cells = <0>;
515           compatible = "st,stm32f4-adc";
516           #io-channel-cells = <1>;
519           interrupt-parent = <&adc123>;
521           st,adc-channels = <8>;
523           dma-names = "rx";
524           assigned-resolution-bits = <8>;
530   - |
532     // - channels 0 & 1 as single-ended
533     // - channels 2 & 3 as differential (with resp. 6 & 7 negative inputs)
534       #include <dt-bindings/interrupt-controller/arm-gic.h>
535       #include <dt-bindings/clock/stm32mp1-clks.h>
537         compatible = "st,stm32mp1-adc-core";
542         clock-names = "bus", "adc";
543         booster-supply = <&booster>;
544         vdd-supply = <&vdd>;
545         vdda-supply = <&vdda>;
546         vref-supply = <&vref>;
547         st,syscfg = <&syscfg>;
548         interrupt-controller;
549         #interrupt-cells = <1>;
550         #address-cells = <1>;
551         #size-cells = <0>;
553           compatible = "st,stm32mp1-adc";
554           #io-channel-cells = <1>;
556           interrupt-parent = <&adc12>;
558           st,adc-channels = <0 1>;
559           st,adc-diff-channels = <2 6>, <3 7>;
560           st,min-sample-time-nsecs = <5000>;
562           dma-names = "rx";
568   - |
570     // - internal channels 13, 14, 15.
571       #include <dt-bindings/interrupt-controller/arm-gic.h>
572       #include <dt-bindings/clock/stm32mp1-clks.h>
574         compatible = "st,stm32mp1-adc-core";
579         clock-names = "bus", "adc";
580         booster-supply = <&booster>;
581         vdd-supply = <&vdd>;
582         vdda-supply = <&vdda>;
583         vref-supply = <&vref>;
584         st,syscfg = <&syscfg>;
585         interrupt-controller;
586         #interrupt-cells = <1>;
587         #address-cells = <1>;
588         #size-cells = <0>;
590           compatible = "st,stm32mp1-adc";
591           #io-channel-cells = <1>;
594           #address-cells = <1>;
595           #size-cells = <0>;
599             st,min-sample-time-ns = <9000>;
604             st,min-sample-time-ns = <9000>;
609             st,min-sample-time-ns = <9000>;