Lines Matching +full:axi +full:- +full:adc
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/adi,axi-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AXI ADC IP core
10 - Michael Hennerich <michael.hennerich@analog.com>
13 Analog Devices Generic AXI ADC IP core for interfacing an ADC device
17 interface for the actual ADC, while this IP core will interface
18 to the data-lines of the ADC and handle the streaming of data into
26 - adi,axi-adc-10.0.a
37 dma-names:
39 - const: rx
41 adi,adc-dev:
44 A reference to a the actual ADC to which this FPGA ADC interfaces to.
47 '#io-backend-cells':
51 - compatible
52 - dmas
53 - reg
54 - clocks
59 - |
60 axi-adc@44a00000 {
61 compatible = "adi,axi-adc-10.0.a";
64 dma-names = "rx";
66 #io-backend-cells = <0>;