bindings/gpu/nvidia%2Cgk20a.txt

4 - compatible: "nvidia,<gpu>"
6   - nvidia,gk20a
7   - nvidia,gm20b
8   - nvidia,gp10b
9   - nvidia,gv11b
10 - reg: Physical base address and length of the controller's registers.
12   - first entry for bar0
13   - second entry for bar1
14 - interrupts: Must contain an entry for each entry in interrupt-names.
15   See ../interrupt-controller/interrupts.txt for details.
16 - interrupt-names: Must include the following entries:
17   - stall
18   - nonstall
19 - vdd-supply: regulator for supply voltage. Only required for GPUs not using
21 - clocks: Must contain an entry for each entry in clock-names.
22   See ../clocks/clock-bindings.txt for details.
23 - clock-names: Must include the following entries:
24   - gpu
25   - pwr
28   - ref
31   - fuse
32 - resets: Must contain an entry for each entry in reset-names.
34 - reset-names: Must include the following entries:
35   - gpu
36 - power-domains: GPUs that make use of power domains can define this property
37   instead of vdd-supply. Currently "nvidia,gp10b" makes use of this.
40 - iommus: A reference to the IOMMU. See ../iommu/iommu.txt for details.
50 		interrupt-names = "stall", "nonstall";
51 		vdd-supply = <&vdd_gpu>;
54 		clock-names = "gpu", "pwr";
56 		reset-names = "gpu";
57 		iommus = <&mc TEGRA_SWGROUP_GPU>;
68 		interrupt-names = "stall", "nonstall";
72 		clock-names = "gpu", "pwr", "ref";
74 		reset-names = "gpu";
75 		iommus = <&mc TEGRA_SWGROUP_GPU>;
86 		interrupt-names = "stall", "nonstall";
89 		clock-names = "gpu", "pwr";
91 		reset-names = "gpu";
92 		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
93 		iommus = <&smmu TEGRA186_SID_GPU>;
104 		interrupt-names = "stall", "nonstall";
108 		clock-names = "gpu", "pwr", "fuse";
110 		reset-names = "gpu";
111 		dma-coherent;
113 		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
114 		iommus = <&smmu TEGRA194_SID_GPU>;