bindings/gpio/xlnx%2Czynqmp-gpio-modepin.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ZynqMP Mode Pin GPIO controller
10   PS_MODE is 4-bits boot mode pins sampled on POR deassertion. Mode Pin
11   GPIO controller with configurable from numbers of pins (from 0 to 3 per
15   - Mubin Sayyed <mubin.sayyed@amd.com>
16   - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
20     const: xlnx,zynqmp-gpio-modepin
22   gpio-controller: true
24   "#gpio-cells":
30   - compatible
31   - gpio-controller
32   - "#gpio-cells"
37   - |
38     zynqmp-firmware {
39         gpio {
40             compatible = "xlnx,zynqmp-gpio-modepin";
41             gpio-controller;
42             #gpio-cells = <2>;
43             label = "modepin";