bindings/gpio/snps%2Cdw-apb-gpio.yaml

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/snps,dw-apb-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12   GPIO-controller properties as described in this bindings file.
15   - Hoan Tran <hoan@os.amperecomputing.com>
16   - Serge Semin <fancer.lancer@gmail.com>
20     pattern: "^gpio@[0-9a-f]+$"
23     const: snps,dw-apb-gpio
25   "#address-cells":
28   "#size-cells":
37       - description: APB interface clock source
38       - description: DW GPIO debounce reference clock source
40   clock-names:
43       - const: bus
44       - const: db
50   "^gpio-(port|controller)@[0-9a-f]+$":
54         const: snps,dw-apb-gpio-port
59       gpio-controller: true
61       '#gpio-cells':
64       gpio-line-names:
68       gpio-ranges: true
75       snps,nr-gpios:
85           The interrupts to the parent controller raised when GPIOs generate
87           for all GPIOs, specify a single interrupt. If the controller provides
93       interrupt-controller: true
95       '#interrupt-cells':
99       - compatible
100       - reg
101       - gpio-controller
102       - '#gpio-cells'
105       interrupt-controller: [ interrupts ]
112   - compatible
113   - reg
114   - "#address-cells"
115   - "#size-cells"
118   - |
120       compatible = "snps,dw-apb-gpio";
122       #address-cells = <1>;
123       #size-cells = <0>;
125       porta: gpio-port@0 {
126         compatible = "snps,dw-apb-gpio-port";
128         gpio-controller;
129         #gpio-cells = <2>;
130         snps,nr-gpios = <8>;
131         interrupt-controller;
132         #interrupt-cells = <2>;
133         interrupt-parent = <&vic1>;
137       portb: gpio-port@1 {
138         compatible = "snps,dw-apb-gpio-port";
140         gpio-controller;
141         #gpio-cells = <2>;
142         snps,nr-gpios = <8>;