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7 busses, which are then exposed by the device tree. For example, an FSI engine
8 that is an I2C master - the I2C bus can be described by the device tree under
19       /* top-level of FSI bus topology, bound to an FSI master driver and
20        * exposes an FSI bus */
40 not be described; this binding only provides an optional facility for
47 value. It's likely that an implementation-specific compatible value will
59 An optional boolean property can be added to indicate that a particular master
70 for an address identifier. Since these are not a range, no size cells are
71 required. For an example, a slave on link 1, with ID 2, could be represented
79 Each slave provides an address-space, under which the engines are accessible.
109 Here's an example that illustrates:
110  - an FSI master
111    - connected to an FSI slave
112      - that contains an engine that is an I2C master
113        - connected to an I2C EEPROM
135              * it's an I2C master controller, so subnodes describe the
141                 /* Engine-specific data. In this case, we're describing an
148                 /* I2C endpoint device: an Atmel EEPROM */