bindings/fpga/fpga-region.yaml

1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Michal Simek <michal.simek@amd.com>
14    - Introduction
15    - Terminology
16    - Sequence
17    - FPGA Region
18    - Supported Use Models
19    - Constraints
89       ----------------       ----------------------------------
92       |          ----|       |       -----------    --------  |
94       |          | W |       |   |   -----------    --------  |
96       |          | B |<=====>|<==|   -----------    --------  |
98       |          | I |       |   |   -----------    --------  |
100       |          | G |       |   |   -----------    --------  |
102       |          ----|       |       -----------    --------  |
104       ----------------       ----------------------------------
106   Figure 1: An FPGA set up with a base image that created three regions.  Each
107   region (PRR0-2) gets its own split of the busses that is independently gated by
108   a soft logic bridge (Bridge0-2) in the FPGA.  The contents of each PRR can be
118    1. Disable appropriate FPGA bridges.
137    * image-specific information needed to the programming.
144   If the live tree shows a "firmware-name" property or child nodes under an FPGA
146   and adds the "firmware-name" property is taken as a request to reprogram the
169   region is getting reconfigured (see Figure 1 above).  During PR, the FPGA's
192      fpga-bridges property in the FPGA region or in the device tree overlay.
207   constraints required to make partial reconfiguration work[1] [2] [3], but a few
217   --
218   [1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf
219   [2] tspace.library.utoronto.ca/bitstream/1807/67932/1/Byma_Stuart_A_201411_MAS_thesis.pdf
224     pattern: "^fpga-region(@.*|-([0-9]|[1-9][0-9]+))?$"
227     const: fpga-region
230     maxItems: 1
233   "#address-cells": true
234   "#size-cells": true
236   config-complete-timeout-us:
241   encrypted-fpga-config:
246   external-fpga-config:
251   firmware-name:
252     maxItems: 1
260   fpga-bridges:
261     $ref: /schemas/types.yaml#/definitions/phandle-array
266       If the fpga-region is  the child of an fpga-bridge, the list should not
269   fpga-mgr:
273       inherit this property from their ancestor regions.  An fpga-mgr property
276   partial-fpga-config:
282   region-freeze-timeout-us:
287   region-unfreeze-timeout-us:
293   - compatible
294   - fpga-mgr
300   - |
304     fpga_region0: fpga-region@0 {
305       compatible = "fpga-region";
307       #address-cells = <1>;
308       #size-cells = <1>;
309       fpga-mgr = <&fpga_mgr0>;
313       firmware-name = "zynq-gpio.bin";
314       gpio@40000000 {
315         compatible = "xlnx,xps-gpio-1.00.a";
317         gpio-controller;
318         #gpio-cells = <2>;
322   - |
326     fpga_region1: fpga-region@0 {
327       compatible = "fpga-region";
330       #address-cells = <1>;
331       #size-cells = <1>;
332       fpga-mgr = <&fpga_mgr1>;
333       fpga-bridges = <&fpga_bridge1>;
334       partial-fpga-config;
337       firmware-name = "zynq-gpio-partial.bin";
339         compatible = "fixed-factor-clock";
341         #clock-cells = <0>;
342         clock-div = <2>;
343         clock-mult = <1>;
346         compatible = "simple-bus";
347         #address-cells = <1>;
348         #size-cells = <1>;
350         gpio@40000000 {
351           compatible = "xlnx,xps-gpio-1.00.a";
353           #gpio-cells = <2>;
354           gpio-controller;