bindings/fpga/fpga-region.yaml

65    * FPGA Bridges gate bus signals between a host and FPGA.
66    * FPGA Bridges should be disabled while the FPGA is being programmed to
68    * FPGA bridges may be actual hardware or soft logic on an FPGA.
69    * During Full Reconfiguration, hardware bridges between the host and FPGA
74      buses, eliminating the need to show the hardware FPGA bridges in the
118    1. Disable appropriate FPGA bridges.
120    3. Enable the FPGA bridges.
125   will disable the bridges.
136    * FPGA Bridges
152   FPGA region will be the child of one of the hardware bridges (the bridge that
155   list of phandles to the additional hardware FPGA Bridges.
158   These FPGA regions are children of FPGA bridges which are then children of the
167   FPGA Regions do not inherit their ancestor FPGA regions' bridges.  This prevents
168   shutting down bridges that are upstream from the other active regions while one
170   hardware bridges remain enabled.  The PR regions' bridges will be FPGA bridges
177   In all cases the live DT must have the FPGA Manager, FPGA Bridges (if any), and
181    * No FPGA Bridges
183      bridges behind the scenes.  No FPGA Bridge devices are needed for full
186    * Full reconfiguration with hardware bridges
187      In this case, there are hardware bridges between the processor and FPGA that
189      applied, the live DT must include the FPGA Manager, FPGA Bridges, and a
191      register access to the FPGA.  Additional bridges may be listed in a
192      fpga-bridges property in the FPGA region or in the device tree overlay.
194    * Partial reconfiguration with bridges in the FPGA
197      bridges need to exist in the FPGA that can gate the buses going to each FPGA
200      PRR's with FPGA bridges.  The device tree should have an FPGA region for each
215   FPGA Bridges that exist on the FPGA fabric prior to the partial reconfiguration.
260   fpga-bridges:
263       Should contain a list of phandles to FPGA Bridges that must be
265       This property is optional if the FPGA Manager handles the bridges.
284       The maximum time in microseconds to wait for bridges to successfully
289       The maximum time in microseconds to wait for bridges to successfully
302      * Full Reconfiguration without Bridges with DT overlay
333       fpga-bridges = <&fpga_bridge1>;