bindings/fpga/fpga-region.yaml

4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
7 title: FPGA Region
17    - FPGA Region
46   Partial Reconfiguration Region (PRR)
53      into a PRR must fit and must use a subset of the region's connections.
54    * The busses within the FPGA are split such that each region gets its own
71    * During Partial Reconfiguration of a specific region, that region's bridge
107   region (PRR0-2) gets its own split of the busses that is independently gated by
115   When a DT overlay that targets an FPGA Region is applied, the FPGA Region will
124   When the overlay is removed, the child nodes will be removed and the FPGA Region
128   FPGA Region
132   Region brings together the elements needed to program on a running system and
143   An FPGA Region that exists in the live Device Tree reflects the current state.
145   Region, the FPGA already has been programmed.  A DTO that targets an FPGA Region
150   The base FPGA Region in the device tree represents the FPGA and supports full
152   FPGA region will be the child of one of the hardware bridges (the bridge that
154   one bridge to control during FPGA programming, the region will also contain a
157   For partial reconfiguration (PR), each PR region will have an FPGA Region.
159   base FPGA region.  The "Full Reconfiguration to add PRR's" example below shows
162   If an FPGA Region does not specify an FPGA Manager, it will inherit the FPGA
163   Manager specified by its ancestor FPGA Region.  This supports both the case
165   a different FPGA Manager is used for each region.
169   region is getting reconfigured (see Figure 1 above).  During PR, the FPGA's
178   a FPGA Region.  The target of the Device Tree Overlay is the FPGA Region.  Some
190      FPGA Region.  The FPGA Region is the child of the bridge that allows
192      fpga-bridges property in the FPGA region or in the device tree overlay.
198      region while the buses are enabled for other sections.  Before any partial
200      PRR's with FPGA bridges.  The device tree should have an FPGA region for each
211   or region it is designed to go into.
224     pattern: "^fpga-region(@.*|-([0-9]|[1-9][0-9]+))?$"
227     const: fpga-region
239       mode after the region has been programmed.
257       If this property is in an overlay targeting an FPGA region, it is
266       If the fpga-region is  the child of an fpga-bridge, the list should not
274       in a region will override any inherited FPGA manager.
282   region-freeze-timeout-us:
285       become disabled before the region has been programmed.
287   region-unfreeze-timeout-us:
290       become enabled after the region has been programmed.
304     fpga_region0: fpga-region@0 {
305       compatible = "fpga-region";
326     fpga_region1: fpga-region@0 {
327       compatible = "fpga-region";