bindings/firmware/nvidia%2Ctegra186-bpmp.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Boot and Power Management Processor (BPMP)
10   - Thierry Reding <thierry.reding@gmail.com>
11   - Jon Hunter <jonathanh@nvidia.com>
14   The BPMP is a specific processor in Tegra chip, which is designed for
16   management, and reset control tasks from the CPU. The binding document
17   defines the resources that would be used by the BPMP firmware driver,
19   CPU and BPMP.
25     - .../mailbox/mailbox.txt
26     - .../mailbox/nvidia,tegra186-hsp.yaml
32     - .../clock/clock-bindings.txt
33     - <dt-bindings/clock/tegra186-clock.h>
34     - ../power/power-domain.yaml
35     - <dt-bindings/power/tegra186-powergate.h>
36     - .../reset/reset.txt
37     - <dt-bindings/reset/tegra186-reset.h>
39   The BPMP implements some services which must be represented by
43   BPMP node.
45   Software can determine whether a child node of the BPMP node
49   provide configuration information regarding the BPMP itself, although
52   The BPMP firmware defines no single global name-/numbering-space for
54   distinct from the numbering scheme for any other service the BPMP may
56   device nodes will have no reg property, and the BPMP node will have no
57   "#address-cells" or "#size-cells" property.
59   The shared memory area for the IPC TX and RX between CPU and BPMP are
63   See "../reserved-memory/nvidia,tegra264-bpmp-shmem.yaml" for bindings for
69       - items:
70           - enum:
71               - nvidia,tegra194-bpmp
72               - nvidia,tegra234-bpmp
73           - const: nvidia,tegra186-bpmp
74       - const: nvidia,tegra186-bpmp
78       communicate with the BPMP.
82     description: List of the phandle to the TX and RX shared memory area
83       that the IPC between CPU and BPMP is based on.
87   memory-region:
89       CPU-NS and BPMP.
92   "#clock-cells":
95   "#power-domain-cells":
98   "#reset-cells":
103       - description: memory read client
104       - description: memory write client
105       - description: DMA read client
106       - description: DMA write client
108   interconnect-names:
110       - const: read
111       - const: write
112       - const: dma-mem # dma-read
113       - const: dma-write
127   - required:
128       - memory-region
129   - required:
130       - shmem
133   - compatible
134   - mboxes
135   - "#clock-cells"
136   - "#power-domain-cells"
137   - "#reset-cells"
140   - |
141     #include <dt-bindings/interrupt-controller/arm-gic.h>
142     #include <dt-bindings/mailbox/tegra186-hsp.h>
143     #include <dt-bindings/memory/tegra186-mc.h>
146         compatible = "nvidia,tegra186-hsp";
149         interrupt-names = "doorbell";
150         #mbox-cells = <2>;
154         compatible = "nvidia,tegra186-sysram", "mmio-sram";
156         #address-cells = <1>;
157         #size-cells = <1>;
162             label = "cpu-bpmp-tx";
168             label = "cpu-bpmp-rx";
173     bpmp {
174         compatible = "nvidia,tegra186-bpmp";
179         interconnect-names = "read", "write", "dma-mem", "dma-write";
183         #clock-cells = <1>;
184         #power-domain-cells = <1>;
185         #reset-cells = <1>;
188             compatible = "nvidia,tegra186-bpmp-i2c";
189             nvidia,bpmp-bus-id = <5>;
190             #address-cells = <1>;
191             #size-cells = <0>;
195             compatible = "nvidia,tegra186-bpmp-thermal";
196             #thermal-sensor-cells = <1>;
200   - |
201     #include <dt-bindings/mailbox/tegra186-hsp.h>
203     bpmp {
204         compatible = "nvidia,tegra186-bpmp";
209         interconnect-names = "read", "write", "dma-mem", "dma-write";
211         memory-region = <&dram_cpu_bpmp_mail>;
212         #clock-cells = <1>;
213         #power-domain-cells = <1>;
214         #reset-cells = <1>;