bindings/firmware/intel%2Cstratix10-svc.txt

3 Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard
12 exception layers must channel through the EL3 software whenever it needs
22 -------------------
26 - compatible: "intel,stratix10-svc" or "intel,agilex-svc"
27 - method: smc or hvc
28         smc - Secure Monitor Call
29         hvc - Hypervisor Call
30 - memory-region:
32 	Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
36 -------
38 	reserved-memory {
39                 #address-cells = <2>;
40                 #size-cells = <2>;
44                         compatible = "shared-dma-pool";
47                         no-map;
53 			compatible = "intel,stratix10-svc";
55 			memory-region = <&service_reserved>;