bindings/dsp/mediatek%2Cmt8195-dsp.yaml

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dsp/mediatek,mt8195-dsp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - YC Hung <yc.hung@mediatek.com>
14   advanced pre- and post- audio processing.
18     const: mediatek,mt8195-dsp
22       - description: Address and size of the DSP Cfg registers
23       - description: Address and size of the DSP SRAM
25   reg-names:
27       - const: cfg
28       - const: sram
32       - description: mux for audio dsp clock
33       - description: 26M clock
34       - description: mux for audio dsp local bus
35       - description: default audio dsp local bus clock source
36       - description: clock gate for audio dsp clock
37       - description: mux for audio dsp access external bus
39   clock-names:
41       - const: adsp_sel
42       - const: clk26m_ck
43       - const: audio_local_bus
44       - const: mainpll_d7_d2
45       - const: scp_adsp_audiodsp
46       - const: audio_h
48   power-domains:
53       - description: mailbox for receiving audio DSP requests.
54       - description: mailbox for transmitting requests to audio DSP.
56   mbox-names:
58       - const: rx
59       - const: tx
61   memory-region:
63       - description: dma buffer between host and DSP.
64       - description: DSP system memory.
67   - compatible
68   - reg
69   - reg-names
70   - clocks
71   - clock-names
72   - memory-region
73   - power-domains
74   - mbox-names
75   - mboxes
80   - |
81     #include <dt-bindings/interrupt-controller/arm-gic.h>
82     #include <dt-bindings/interrupt-controller/irq.h>
84        compatible =  "mediatek,mt8195-dsp";
87        reg-names = "cfg", "sram";
94        clock-names = "adsp_sel",
100        memory-region = <&adsp_dma_mem_reserved>,
102        power-domains = <&spm 6>; //MT8195_POWER_DOMAIN_ADSP
103        mbox-names = "rx", "tx";