dma/xilinx/xilinx_dma.txt

2 It can be configured to have one channel or two channels. If configured
3 as two channels, one is to transmit to the video device and another is
7 target devices. It can be configured to have one channel or two channels.
8 If configured as two channels, one is to transmit to the device and another
11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
12 address and a memory-mapped destination address.
19 - compatible: Should be one of-
20 		"xlnx,axi-vdma-1.00.a"
21 		"xlnx,axi-dma-1.00.a"
22 		"xlnx,axi-cdma-1.00.a"
23 		"xlnx,axi-mcdma-1.00.a"
24 - #dma-cells: Should be <1>, see "dmas" property below
25 - reg: Should contain VDMA registers location and length.
26 - xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits).
27 - dma-ranges: Should be as the following <dma_addr cpu_addr max_len>.
28 - dma-channel child node: Should have at least one channel and can have up to
29 	two channels per device. This node specifies the properties of each
30 	DMA channel (see child node properties below).
31 - clocks: Input clock specifier. Refer to common clock bindings.
32 - clock-names: List of input clocks
45 - xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.
48 - xlnx,sg-length-width: Should be set to the width in bits of the length
54 - xlnx,axistream-connected: Tells whether DMA is connected to AXI stream IP.
55 - xlnx,irq-delay: Tells the interrupt delay timeout value. Valid range is from
56 	0-255. Setting this value to zero disables the delay timer interrupt.
59 - xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
62 	{2}, flush mm2s channel
63 	{3}, flush s2mm channel
66 - compatible:
67 	For VDMA: It should be either "xlnx,axi-vdma-mm2s-channel" or
68 	"xlnx,axi-vdma-s2mm-channel".
69 	For CDMA: It should be "xlnx,axi-cdma-channel".
70 	For AXIDMA and MCDMA: It should be either "xlnx,axi-dma-mm2s-channel"
71 	or "xlnx,axi-dma-s2mm-channel".
72 - interrupts: Should contain per channel VDMA interrupts.
73 - xlnx,datawidth: Should contain the stream data width, take values
77 - xlnx,include-dre: Tells hardware is configured for Data
80 - xlnx,genlock-mode: Tells Genlock synchronization is
82 - xlnx,enable-vert-flip: Tells vertical flip is
85 - dma-channels: Number of dma channels in child node.
91 	compatible = "xlnx,axi-vdma-1.00.a";
94 	dma-ranges = <0x00000000 0x00000000 0x40000000>;
95 	xlnx,num-fstores = <0x8>;
96 	xlnx,flush-fsync = <0x1>;
99 	clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
101 	dma-channel@40030000 {
102 		compatible = "xlnx,axi-vdma-mm2s-channel";
106 	dma-channel@40030030 {
107 		compatible = "xlnx,axi-vdma-s2mm-channel";
117 - dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs,
118 	where Channel ID is '0' for write/tx and '1' for read/rx
119 	channel. For MCMDA, MM2S channel(write/tx) ID start from
120 	'0' and is in [0-15] range. S2MM channel(read/rx) ID start
121 	from '16' and is in [16-31] range. These channels ID are
124 - dma-names: a list of DMA channel names, one per "dmas" entry
130 	compatible ="xlnx,axi-vdma-test-1.00.a";
133 	dma-names = "vdma0", "vdma1";