dma/stm32/st%2Cstm32-mdma.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-mdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   The STM32 MDMA is a general-purpose direct memory access controller capable of
13   described in the dma.txt file, using a five-cell specifier for each channel:
22       -bit 0-1: Source increment mode
26       -bit 2-3: Destination increment mode
30       -bit 8-9: Source increment offset size
32         0x1: half-word (16bit)
34         0x3: double-word (64bit)
35       -bit 10-11: Destination increment offset size
37         0x1: half-word (16bit)
39         0x3: double-word (64bit)
40       -bit 25-18: The number of bytes to be transferred in a single transfer
42       -bit 29:28: Trigger Mode
53   - Amelie Delaunay <amelie.delaunay@foss.st.com>
56   - $ref: /schemas/dma/dma-controller.yaml#
59   "#dma-cells":
63     const: st,stm32h7-mdma
77   st,ahb-addr-masks:
78     $ref: /schemas/types.yaml#/definitions/uint32-array
79     description: Array of u32 mask to list memory devices addressed via AHB bus.
82   - compatible
83   - reg
84   - clocks
85   - interrupts
90   - |
91     #include <dt-bindings/interrupt-controller/arm-gic.h>
92     #include <dt-bindings/clock/stm32mp1-clks.h>
93     #include <dt-bindings/reset/stm32mp1-resets.h>
94     dma-controller@52000000 {
95       compatible = "st,stm32h7-mdma";
100       #dma-cells = <5>;
101       dma-channels = <16>;
102       dma-requests = <32>;
103       st,ahb-addr-masks = <0x20000000>, <0x00000000>;