bindings/dma/snps%2Cdw-axi-dmac.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare AXI DMA Controller
10   - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
13   Synopsys DesignWare AXI DMA Controller DT Binding
16   - $ref: dma-controller.yaml#
21       - snps,axi-dma-1.01a
22       - intel,kmb-axi-dma
23       - starfive,jh7110-axi-dma
24       - starfive,jh8100-axi-dma
29       - description: Address range of the DMAC registers
30       - description: Address range of the DMAC APB registers
32   reg-names:
34       - const: axidma_ctrl_regs
35       - const: axidma_apb_regs
39       If the IP-core synthesis parameter DMAX_INTR_IO_TYPE is set to 1, this
40       will be per-channel interrupts. Otherwise, this is a single combined IRQ
47       - description: Bus Clock
48       - description: Module Clock
50   clock-names:
52       - const: core-clk
53       - const: cfgr-clk
55   '#dma-cells':
58   dma-channels:
66   snps,dma-masters:
68       Number of AXI masters supported by the hardware.
72   snps,data-width:
74       AXI data width supported by hardware.
75       (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
82     $ref: /schemas/types.yaml#/definitions/uint32-array
86   snps,block-size:
89     $ref: /schemas/types.yaml#/definitions/uint32-array
93   snps,axi-max-burst-len:
95       Restrict master AXI burst length by value specified in this property.
96       If this property is missing the maximum AXI burst length supported by
103   - compatible
104   - reg
105   - clocks
106   - clock-names
107   - interrupts
108   - '#dma-cells'
109   - dma-channels
110   - snps,dma-masters
111   - snps,data-width
112   - snps,priority
113   - snps,block-size
120           - starfive,jh7110-axi-dma
126         - description: AXI reset line
127         - description: AHB reset line
128         - description: module reset
137   - |
138     #include <dt-bindings/interrupt-controller/arm-gic.h>
139     #include <dt-bindings/interrupt-controller/irq.h>
140     /* example with snps,dw-axi-dmac */
141     dma-controller@80000 {
142         compatible = "snps,axi-dma-1.01a";
145         clock-names = "core-clk", "cfgr-clk";
146         interrupt-parent = <&intc>;
148         #dma-cells = <1>;
149         dma-channels = <4>;
150         snps,dma-masters = <2>;
151         snps,data-width = <3>;
152         snps,block-size = <4096 4096 4096 4096>;
154         snps,axi-max-burst-len = <16>;