bindings/dma/renesas%2Crz-dmac.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Biju Das <biju.das.jz@bp.renesas.com>
13   - $ref: dma-controller.yaml#
18       - enum:
19           - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five
20           - renesas,r9a07g044-dmac # RZ/G2{L,LC}
21           - renesas,r9a07g054-dmac # RZ/V2L
22           - renesas,r9a08g045-dmac # RZ/G3S
23       - const: renesas,rz-dmac
27       - description: Control and channel register block
28       - description: DMA extended resource selector block
33   interrupt-names:
35       - const: error
36       - const: ch0
37       - const: ch1
38       - const: ch2
39       - const: ch3
40       - const: ch4
41       - const: ch5
42       - const: ch6
43       - const: ch7
44       - const: ch8
45       - const: ch9
46       - const: ch10
47       - const: ch11
48       - const: ch12
49       - const: ch13
50       - const: ch14
51       - const: ch15
55       - description: DMA main clock
56       - description: DMA register access clock
58   clock-names:
60       - const: main
61       - const: register
63   '#dma-cells':
69       bits[0:9] - Specifies MID/RID value
70       bit[10] - Specifies DMA request high enable (HIEN)
71       bit[11] - Specifies DMA request detection type (LVL)
72       bits[12:14] - Specifies DMAACK output mode (AM)
73       bit[15] - Specifies Transfer Mode (TM)
75   dma-channels:
78   power-domains:
83       - description: Reset for DMA ARESETN reset terminal
84       - description: Reset for DMA RST_ASYNC reset terminal
86   reset-names:
88       - const: arst
89       - const: rst_async
92   - compatible
93   - reg
94   - interrupts
95   - interrupt-names
96   - clocks
97   - clock-names
98   - '#dma-cells'
99   - dma-channels
100   - power-domains
101   - resets
102   - reset-names
107   - |
108     #include <dt-bindings/interrupt-controller/arm-gic.h>
109     #include <dt-bindings/clock/r9a07g044-cpg.h>
111     dmac: dma-controller@11820000 {
112         compatible = "renesas,r9a07g044-dmac",
113                      "renesas,rz-dmac";
133         interrupt-names = "error",
134                           "ch0", "ch1", "ch2", "ch3",
140         clock-names = "main", "register";
141         power-domains = <&cpg>;
144         reset-names = "arst", "rst_async";
145         #dma-cells = <1>;
146         dma-channels = <16>;