bindings/display/st%2Cstm32mp25-lvds.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/st,stm32mp25-lvds.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
11   - Yannick Fertre <yannick.fertre@foss.st.com>
15   LVDS protocol: it maps the pixels received from the upstream Pixel-DMA (LTDC)
19     - LVDS host: handles the LVDS protocol (FPD / OpenLDI) and maps its input
21     - LVDS PHY: parallelize the data and drives the LVDS data lanes
22     - LVDS wrapper: handles top-level settings
24   The LVDS controller driver supports the following high-level features:
25     - FDP-Link-I and OpenLDI (v0.95) protocols
26     - Single-Link or Dual-Link operation
27     - Single-Display or Double-Display (with the same content duplicated on both)
28     - Flexible Bit-Mapping, including JEIDA and VESA
29     - RGB888 or RGB666 output
30     - Synchronous design, with one input pixel per clock cycle
34     const: st,stm32mp25-lvds
36   "#clock-cells":
46       - description: APB peripheral clock
47       - description: Reference clock for the internal PLL
49   clock-names:
51       - const: pclk
52       - const: ref
72       - port@0
73       - port@1
76   - compatible
77   - "#clock-cells"
78   - reg
79   - clocks
80   - clock-names
81   - resets
82   - ports
87   - |
88     #include <dt-bindings/clock/st,stm32mp25-rcc.h>
89     #include <dt-bindings/reset/st,stm32mp25-rcc.h>
92         compatible = "st,stm32mp25-lvds";
94         #clock-cells = <0>;
96         clock-names = "pclk", "ref";
100             #address-cells = <1>;
101             #size-cells = <0>;
106                    remote-endpoint = <&ltdc_ep1_out>;
113                    remote-endpoint = <&lvds_panel_in>;