Lines Matching +full:model +full:- +full:dependent
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/renesas,rzg2l-du.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biju Das <biju.das.jz@bp.renesas.com>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
20 - enum:
21 - renesas,r9a07g043u-du # RZ/G2UL
22 - renesas,r9a07g044-du # RZ/G2{L,LC}
23 - items:
24 - enum:
25 - renesas,r9a07g054-du # RZ/V2L
26 - const: renesas,r9a07g044-du # RZ/G2L fallback
36 - description: Main clock
37 - description: Register access clock
38 - description: Video clock
40 clock-names:
42 - const: aclk
43 - const: pclk
44 - const: vclk
49 power-domains:
57 model-dependent. Each port shall have a single endpoint.
60 "^port@[0-1]$":
67 $ref: /schemas/types.yaml#/definitions/phandle-array
70 - description: phandle to VSP instance that serves the DU channel
71 - description: Channel index identifying the LIF instance in that VSP
77 - compatible
78 - reg
79 - interrupts
80 - clocks
81 - clock-names
82 - resets
83 - power-domains
84 - ports
85 - renesas,vsps
90 - if:
94 const: renesas,r9a07g043u-du
103 - port@0
114 - port@0
115 - port@1
119 - |
120 #include <dt-bindings/clock/r9a07g044-cpg.h>
121 #include <dt-bindings/interrupt-controller/arm-gic.h>
124 compatible = "renesas,r9a07g044-du";
130 clock-names = "aclk", "pclk", "vclk";
132 power-domains = <&cpg>;
137 #address-cells = <1>;
138 #size-cells = <0>;
143 remote-endpoint = <&dsi0_in>;