Lines Matching full:dispcc
82 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
98 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
100 power-domains = <&dispcc MDSS_GDSC>;
102 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
105 <&dispcc DISP_CC_MDSS_MDP_CLK>;
126 <&dispcc DISP_CC_MDSS_AHB_CLK>,
127 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
128 <&dispcc DISP_CC_MDSS_MDP_CLK>,
129 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
137 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
198 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
199 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
200 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
201 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
202 <&dispcc DISP_CC_MDSS_AHB_CLK>,
211 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
212 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
274 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
287 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
288 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
289 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
290 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
291 <&dispcc DISP_CC_MDSS_AHB_CLK>,
300 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
301 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
344 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,