Lines Matching full:dispcc
82 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
101 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
103 power-domains = <&dispcc MDSS_GDSC>;
105 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
108 <&dispcc DISP_CC_MDSS_MDP_CLK>;
129 <&dispcc DISP_CC_MDSS_AHB_CLK>,
130 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
131 <&dispcc DISP_CC_MDSS_MDP_CLK>,
132 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
140 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
206 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
207 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
208 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
209 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
210 <&dispcc DISP_CC_MDSS_AHB_CLK>,
219 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
220 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
287 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
301 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
302 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
303 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
304 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
305 <&dispcc DISP_CC_MDSS_AHB_CLK>,
314 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
315 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
358 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,