display/msm/qcom%2Csm8450-dpu.yaml

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
12 $ref: /schemas/display/msm/dpu-common.yaml#
16     const: qcom,sm8450-dpu
20       - description: Address offset and size for mdp register set
21       - description: Address offset and size for vbif register set
23   reg-names:
25       - const: mdp
26       - const: vbif
30       - description: Display hf axi
31       - description: Display sf axi
32       - description: Display ahb
33       - description: Display lut
34       - description: Display core
35       - description: Display vsync
37   clock-names:
39       - const: bus
40       - const: nrt_bus
41       - const: iface
42       - const: lut
43       - const: core
44       - const: vsync
47   - compatible
48   - reg
49   - reg-names
50   - clocks
51   - clock-names
56   - |
57     #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
58     #include <dt-bindings/clock/qcom,gcc-sm8450.h>
59     #include <dt-bindings/interrupt-controller/arm-gic.h>
60     #include <dt-bindings/interconnect/qcom,sm8450.h>
61     #include <dt-bindings/power/qcom,rpmhpd.h>
63     display-controller@ae01000 {
64         compatible = "qcom,sm8450-dpu";
67         reg-names = "mdp", "vbif";
75         clock-names = "bus",
82         assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
83         assigned-clock-rates = <19200000>;
85         operating-points-v2 = <&mdp_opp_table>;
86         power-domains = <&rpmhpd RPMHPD_MMCX>;
88         interrupt-parent = <&mdss>;
92             #address-cells = <1>;
93             #size-cells = <0>;
98                     remote-endpoint = <&dsi0_in>;
105                     remote-endpoint = <&dsi1_in>;
110         mdp_opp_table: opp-table {
111             compatible = "operating-points-v2";
113             opp-172000000{
114                 opp-hz = /bits/ 64 <172000000>;
115                 required-opps = <&rpmhpd_opp_low_svs_d1>;
118             opp-200000000 {
119                 opp-hz = /bits/ 64 <200000000>;
120                 required-opps = <&rpmhpd_opp_low_svs>;
123             opp-325000000 {
124                 opp-hz = /bits/ 64 <325000000>;
125                 required-opps = <&rpmhpd_opp_svs>;
128             opp-375000000 {
129                 opp-hz = /bits/ 64 <375000000>;
130                 required-opps = <&rpmhpd_opp_svs_l1>;
133             opp-500000000 {
134                 opp-hz = /bits/ 64 <500000000>;
135                 required-opps = <&rpmhpd_opp_nom>;