Lines Matching full:dispcc
90 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
106 power-domains = <&dispcc MDSS_GDSC>;
108 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
111 <&dispcc DISP_CC_MDSS_MDP_CLK>;
130 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
132 <&dispcc DISP_CC_MDSS_MDP_CLK>,
133 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
136 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
197 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
198 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
199 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
200 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
201 <&dispcc DISP_CC_MDSS_AHB_CLK>,
210 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
211 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
273 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
287 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
288 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
289 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
290 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
291 <&dispcc DISP_CC_MDSS_AHB_CLK>,
300 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
301 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
344 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,