display/msm/qcom%2Csm8250-dpu.yaml

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8250-dpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8250 Display DPU
10   - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
12 $ref: /schemas/display/msm/dpu-common.yaml#
16     const: qcom,sm8250-dpu
20       - description: Address offset and size for mdp register set
21       - description: Address offset and size for vbif register set
23   reg-names:
25       - const: mdp
26       - const: vbif
30       - description: Display ahb clock
31       - description: Display hf axi clock
32       - description: Display core clock
33       - description: Display vsync clock
35   clock-names:
37       - const: iface
38       - const: bus
39       - const: core
40       - const: vsync
43   - compatible
44   - reg
45   - reg-names
46   - clocks
47   - clock-names
52   - |
53     #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
54     #include <dt-bindings/clock/qcom,gcc-sm8250.h>
55     #include <dt-bindings/interrupt-controller/arm-gic.h>
56     #include <dt-bindings/interconnect/qcom,sm8250.h>
57     #include <dt-bindings/power/qcom,rpmhpd.h>
59     display-controller@ae01000 {
60         compatible = "qcom,sm8250-dpu";
63         reg-names = "mdp", "vbif";
65         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
67                  <&dispcc DISP_CC_MDSS_MDP_CLK>,
68                  <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
69         clock-names = "iface", "bus", "core", "vsync";
71         assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
72         assigned-clock-rates = <19200000>;
74         operating-points-v2 = <&mdp_opp_table>;
75         power-domains = <&rpmhpd RPMHPD_MMCX>;
77         interrupt-parent = <&mdss>;
81             #address-cells = <1>;
82             #size-cells = <0>;
87                     remote-endpoint = <&dsi0_in>;
94                     remote-endpoint = <&dsi1_in>;