Lines Matching +full:phy +full:- +full:dsi +full:- +full:supply
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8150-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
22 - const: qcom,sm8150-mdss
26 - description: Display AHB clock from gcc
27 - description: Display hf axi clock
28 - description: Display sf axi clock
29 - description: Display core clock
31 clock-names:
33 - const: iface
34 - const: bus
35 - const: nrt_bus
36 - const: core
44 interconnect-names:
48 "^display-controller@[0-9a-f]+$":
54 const: qcom,sm8150-dpu
56 "^displayport-controller@[0-9a-f]+$":
63 const: qcom,sm8150-dp
65 "^dsi@[0-9a-f]+$":
72 - const: qcom,sm8150-dsi-ctrl
73 - const: qcom,mdss-dsi-ctrl
75 "^phy@[0-9a-f]+$":
81 const: qcom,dsi-phy-7nm-8150
86 - |
87 #include <dt-bindings/clock/qcom,dispcc-sm8150.h>
88 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
89 #include <dt-bindings/clock/qcom,rpmh.h>
90 #include <dt-bindings/interrupt-controller/arm-gic.h>
91 #include <dt-bindings/interconnect/qcom,sm8150.h>
92 #include <dt-bindings/power/qcom-rpmpd.h>
94 display-subsystem@ae00000 {
95 compatible = "qcom,sm8150-mdss";
97 reg-names = "mdss";
101 interconnect-names = "mdp0-mem", "mdp1-mem";
103 power-domains = <&dispcc MDSS_GDSC>;
109 clock-names = "iface", "bus", "nrt_bus", "core";
112 interrupt-controller;
113 #interrupt-cells = <1>;
117 #address-cells = <1>;
118 #size-cells = <1>;
121 display-controller@ae01000 {
122 compatible = "qcom,sm8150-dpu";
125 reg-names = "mdp", "vbif";
131 clock-names = "iface", "bus", "core", "vsync";
133 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
134 assigned-clock-rates = <19200000>;
136 operating-points-v2 = <&mdp_opp_table>;
137 power-domains = <&rpmhpd SM8150_MMCX>;
139 interrupt-parent = <&mdss>;
143 #address-cells = <1>;
144 #size-cells = <0>;
149 remote-endpoint = <&dsi0_in>;
156 remote-endpoint = <&dsi1_in>;
161 mdp_opp_table: opp-table {
162 compatible = "operating-points-v2";
164 opp-171428571 {
165 opp-hz = /bits/ 64 <171428571>;
166 required-opps = <&rpmhpd_opp_low_svs>;
169 opp-300000000 {
170 opp-hz = /bits/ 64 <300000000>;
171 required-opps = <&rpmhpd_opp_svs>;
174 opp-345000000 {
175 opp-hz = /bits/ 64 <345000000>;
176 required-opps = <&rpmhpd_opp_svs_l1>;
179 opp-460000000 {
180 opp-hz = /bits/ 64 <460000000>;
181 required-opps = <&rpmhpd_opp_nom>;
186 dsi@ae94000 {
187 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
189 reg-names = "dsi_ctrl";
191 interrupt-parent = <&mdss>;
200 clock-names = "byte",
207 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
209 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
211 operating-points-v2 = <&dsi_opp_table>;
212 power-domains = <&rpmhpd SM8150_MMCX>;
215 phy-names = "dsi";
217 #address-cells = <1>;
218 #size-cells = <0>;
221 #address-cells = <1>;
222 #size-cells = <0>;
227 remote-endpoint = <&dpu_intf1_out>;
238 dsi_opp_table: opp-table {
239 compatible = "operating-points-v2";
241 opp-187500000 {
242 opp-hz = /bits/ 64 <187500000>;
243 required-opps = <&rpmhpd_opp_low_svs>;
246 opp-300000000 {
247 opp-hz = /bits/ 64 <300000000>;
248 required-opps = <&rpmhpd_opp_svs>;
251 opp-358000000 {
252 opp-hz = /bits/ 64 <358000000>;
253 required-opps = <&rpmhpd_opp_svs_l1>;
258 dsi0_phy: phy@ae94400 {
259 compatible = "qcom,dsi-phy-7nm-8150";
263 reg-names = "dsi_phy",
267 #clock-cells = <1>;
268 #phy-cells = <0>;
272 clock-names = "iface", "ref";
273 vdds-supply = <&vreg_dsi_phy>;
276 dsi@ae96000 {
277 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
279 reg-names = "dsi_ctrl";
281 interrupt-parent = <&mdss>;
290 clock-names = "byte",
297 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
299 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
301 operating-points-v2 = <&dsi_opp_table>;
302 power-domains = <&rpmhpd SM8150_MMCX>;
305 phy-names = "dsi";
307 #address-cells = <1>;
308 #size-cells = <0>;
311 #address-cells = <1>;
312 #size-cells = <0>;
317 remote-endpoint = <&dpu_intf2_out>;
329 dsi1_phy: phy@ae96400 {
330 compatible = "qcom,dsi-phy-7nm-8150";
334 reg-names = "dsi_phy",
338 #clock-cells = <1>;
339 #phy-cells = <0>;
343 clock-names = "iface", "ref";
344 vdds-supply = <&vreg_dsi_phy>;