Lines Matching full:dispcc
87 #include <dt-bindings/clock/qcom,dispcc-sm8150.h>
103 power-domains = <&dispcc MDSS_GDSC>;
105 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
108 <&dispcc DISP_CC_MDSS_MDP_CLK>;
127 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
129 <&dispcc DISP_CC_MDSS_MDP_CLK>,
130 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
133 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
194 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
195 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
196 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
197 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
198 <&dispcc DISP_CC_MDSS_AHB_CLK>,
207 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
208 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
270 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
284 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
285 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
286 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
287 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
288 <&dispcc DISP_CC_MDSS_AHB_CLK>,
297 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
298 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
341 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,