Lines Matching full:dispcc
82 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
93 power-domains = <&dispcc MDSS_GDSC>;
96 <&dispcc DISP_CC_MDSS_MDP_CLK>;
121 <&dispcc DISP_CC_MDSS_AHB_CLK>,
122 <&dispcc DISP_CC_MDSS_AXI_CLK>,
123 <&dispcc DISP_CC_MDSS_MDP_CLK>,
124 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
160 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
161 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
162 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
163 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
164 <&dispcc DISP_CC_MDSS_AHB_CLK>,
165 <&dispcc DISP_CC_MDSS_AXI_CLK>;
172 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
173 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
216 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
230 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
231 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
232 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
233 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
234 <&dispcc DISP_CC_MDSS_AHB_CLK>,
235 <&dispcc DISP_CC_MDSS_AXI_CLK>;
242 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
243 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
286 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,