Lines Matching +full:adreno +full:- +full:gmu +full:- +full:wrapper
1 # SPDX-License-Identifier: GPL-2.0-only
2 # Copyright 2019-2020, The Linux Foundation, All Rights Reserved
4 ---
6 $id: http://devicetree.org/schemas/display/msm/gmu.yaml#
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
9 title: GMU attached to certain Adreno GPUs
12 - Rob Clark <robdclark@gmail.com>
15 These bindings describe the Graphics Management Unit (GMU) that is attached
16 to members of the Adreno A6xx GPU family. The GMU provides on-device power
23 - items:
24 - pattern: '^qcom,adreno-gmu-[67][0-9][0-9]\.[0-9]$'
25 - const: qcom,adreno-gmu
26 - items:
27 - pattern: '^qcom,adreno-gmu-x[1-9][0-9][0-9]\.[0-9]$'
28 - const: qcom,adreno-gmu
29 - const: qcom,adreno-gmu-wrapper
35 reg-names:
43 clock-names:
49 - description: GMU HFI interrupt
50 - description: GMU interrupt
52 interrupt-names:
54 - const: hfi
55 - const: gmu
57 power-domains:
59 - description: CX power domain
60 - description: GX power domain
62 power-domain-names:
64 - const: cx
65 - const: gx
72 description: Reference to the AOSS side-channel message RAM
74 operating-points-v2: true
76 opp-table:
80 - compatible
81 - reg
82 - reg-names
83 - power-domains
84 - power-domain-names
89 - if:
94 - qcom,adreno-gmu-618.0
95 - qcom,adreno-gmu-630.2
100 - description: Core GMU registers
101 - description: GMU PDC registers
102 - description: GMU PDC sequence registers
103 reg-names:
105 - const: gmu
106 - const: gmu_pdc
107 - const: gmu_pdc_seq
110 - description: GMU clock
111 - description: GPU CX clock
112 - description: GPU AXI clock
113 - description: GPU MEMNOC clock
114 clock-names:
116 - const: gmu
117 - const: cxo
118 - const: axi
119 - const: memnoc
121 - if:
126 - qcom,adreno-gmu-635.0
127 - qcom,adreno-gmu-660.1
132 - description: Core GMU registers
133 - description: Resource controller registers
134 - description: GMU PDC registers
135 reg-names:
137 - const: gmu
138 - const: rscc
139 - const: gmu_pdc
142 - description: GMU clock
143 - description: GPU CX clock
144 - description: GPU AXI clock
145 - description: GPU MEMNOC clock
146 - description: GPU AHB clock
147 - description: GPU HUB CX clock
148 - description: GPU SMMU vote clock
149 clock-names:
151 - const: gmu
152 - const: cxo
153 - const: axi
154 - const: memnoc
155 - const: ahb
156 - const: hub
157 - const: smmu_vote
159 - if:
164 - qcom,adreno-gmu-640.1
169 - description: Core GMU registers
170 - description: GMU PDC registers
171 - description: GMU PDC sequence registers
172 reg-names:
174 - const: gmu
175 - const: gmu_pdc
176 - const: gmu_pdc_seq
178 - if:
183 - qcom,adreno-gmu-650.2
188 - description: Core GMU registers
189 - description: Resource controller registers
190 - description: GMU PDC registers
191 - description: GMU PDC sequence registers
192 reg-names:
194 - const: gmu
195 - const: rscc
196 - const: gmu_pdc
197 - const: gmu_pdc_seq
199 - if:
204 - qcom,adreno-gmu-640.1
205 - qcom,adreno-gmu-650.2
210 - description: GPU AHB clock
211 - description: GMU clock
212 - description: GPU CX clock
213 - description: GPU AXI clock
214 - description: GPU MEMNOC clock
215 clock-names:
217 - const: ahb
218 - const: gmu
219 - const: cxo
220 - const: axi
221 - const: memnoc
223 - if:
228 - qcom,adreno-gmu-730.1
229 - qcom,adreno-gmu-740.1
230 - qcom,adreno-gmu-750.1
231 - qcom,adreno-gmu-x185.1
236 - description: Core GMU registers
237 - description: Resource controller registers
238 - description: GMU PDC registers
239 reg-names:
241 - const: gmu
242 - const: rscc
243 - const: gmu_pdc
246 - description: GPU AHB clock
247 - description: GMU clock
248 - description: GPU CX clock
249 - description: GPU AXI clock
250 - description: GPU MEMNOC clock
251 - description: GMU HUB clock
252 - description: GPUSS DEMET clock
253 clock-names:
255 - const: ahb
256 - const: gmu
257 - const: cxo
258 - const: axi
259 - const: memnoc
260 - const: hub
261 - const: demet
264 - qcom,qmp
266 - if:
270 const: qcom,adreno-gmu-wrapper
275 - description: GMU wrapper register space
276 reg-names:
278 - const: gmu
281 - clocks
282 - clock-names
283 - interrupts
284 - interrupt-names
285 - iommus
286 - operating-points-v2
289 - |
290 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
291 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
292 #include <dt-bindings/interrupt-controller/irq.h>
293 #include <dt-bindings/interrupt-controller/arm-gic.h>
295 gmu: gmu@506a000 {
296 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
301 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
307 clock-names = "gmu", "cxo", "axi", "memnoc";
311 interrupt-names = "hfi", "gmu";
313 power-domains = <&gpucc GPU_CX_GDSC>,
315 power-domain-names = "cx", "gx";
318 operating-points-v2 = <&gmu_opp_table>;
321 gmu_wrapper: gmu@596a000 {
322 compatible = "qcom,adreno-gmu-wrapper";
324 reg-names = "gmu";
325 power-domains = <&gpucc GPU_CX_GDSC>,
327 power-domain-names = "cx", "gx";