display/mediatek/mediatek%2Crdma.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11   - Philipp Zabel <p.zabel@pengutronix.de>
15   data into DMA. It provides real time data to the back-end panel
26       - enum:
27           - mediatek,mt2701-disp-rdma
28           - mediatek,mt8173-disp-rdma
29           - mediatek,mt8183-disp-rdma
30           - mediatek,mt8195-disp-rdma
31       - items:
32           - enum:
33               - mediatek,mt8188-disp-rdma
34           - const: mediatek,mt8195-disp-rdma
35       - items:
36           - enum:
37               - mediatek,mt7623-disp-rdma
38               - mediatek,mt2712-disp-rdma
39           - const: mediatek,mt2701-disp-rdma
40       - items:
41           - enum:
42               - mediatek,mt6795-disp-rdma
43           - const: mediatek,mt8173-disp-rdma
44       - items:
45           - enum:
46               - mediatek,mt8186-disp-rdma
47               - mediatek,mt8192-disp-rdma
48               - mediatek,mt8365-disp-rdma
49           - const: mediatek,mt8183-disp-rdma
51   reg:
57   power-domains:
60       Documentation/devicetree/bindings/power/power-domain.yaml for details.
64       - description: RDMA Clock
71   mediatek,rdma-fifo-size:
76       mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
77       mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
78       mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
82   mediatek,gce-client-reg:
83     description: The register of client driver can be configured by gce with
84       4 arguments defined in this property, such as phandle of gce, subsys id,
85       register offset and size. Each GCE subsys id is mapping to a client
86       defined in the header include/dt-bindings/gce/<chip>-gce.h.
87     $ref: /schemas/types.yaml#/definitions/phandle-array
91   - compatible
92   - reg
93   - interrupts
94   - power-domains
95   - clocks
96   - iommus
101   - |
102     #include <dt-bindings/interrupt-controller/arm-gic.h>
103     #include <dt-bindings/clock/mt8173-clk.h>
104     #include <dt-bindings/power/mt8173-power.h>
105     #include <dt-bindings/gce/mt8173-gce.h>
106     #include <dt-bindings/memory/mt8173-larb-port.h>
109         #address-cells = <2>;
110         #size-cells = <2>;
113             compatible = "mediatek,mt8173-disp-rdma";
114             reg = <0 0x1400e000 0 0x1000>;
116             power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
119             mediatek,rdma-fifo-size = <8192>;
120             mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;