display/mediatek/mediatek%2Covl-2l.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl-2l.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11   - Philipp Zabel <p.zabel@pengutronix.de>
14   Mediatek display overlay 2 layer, namely OVL-2L, provides 2 more layer
16   OVL-2L device node must be siblings to the central MMSYS_CONFIG node.
18   Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
24       - enum:
25           - mediatek,mt8183-disp-ovl-2l
26           - mediatek,mt8192-disp-ovl-2l
27       - items:
28           - enum:
29               - mediatek,mt8186-disp-ovl-2l
30           - const: mediatek,mt8192-disp-ovl-2l
38   power-domains:
41       Documentation/devicetree/bindings/power/power-domain.yaml for details.
45       - description: OVL-2L Clock
50       see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
52   mediatek,gce-client-reg:
56       defined in the header include/dt-bindings/gce/<chip>-gce.h.
57     $ref: /schemas/types.yaml#/definitions/phandle-array
61   - compatible
62   - reg
63   - interrupts
64   - power-domains
65   - clocks
66   - iommus
71   - |
72     #include <dt-bindings/interrupt-controller/arm-gic.h>
73     #include <dt-bindings/clock/mt8183-clk.h>
74     #include <dt-bindings/power/mt8183-power.h>
75     #include <dt-bindings/gce/mt8183-gce.h>
76     #include <dt-bindings/memory/mt8183-larb-port.h>
79         #address-cells = <2>;
80         #size-cells = <2>;
83             compatible = "mediatek,mt8183-disp-ovl-2l";
86             power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
89             mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;