display/mediatek/mediatek%2Cdsc.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11   - Philipp Zabel <p.zabel@pengutronix.de>
17   video bit stream. DSC is designed for real-time systems with
18   real-time compression, transmission, decompression and Display.
23       - enum:
24           - mediatek,mt8195-disp-dsc
26   reg:
34       - description: DSC Wrapper Clock
36   power-domains:
39       Documentation/devicetree/bindings/power/power-domain.yaml for details.
41   mediatek,gce-client-reg:
43       The register of client driver can be configured by gce with 4 arguments
44       defined in this property, such as phandle of gce, subsys id,
47       register which is defined in the gce header
48       include/dt-bindings/gce/<chip>-gce.h.
49     $ref: /schemas/types.yaml#/definitions/phandle-array
53   - compatible
54   - reg
55   - interrupts
56   - power-domains
57   - clocks
62   - |
63     #include <dt-bindings/interrupt-controller/arm-gic.h>
64     #include <dt-bindings/clock/mt8195-clk.h>
65     #include <dt-bindings/power/mt8195-power.h>
66     #include <dt-bindings/gce/mt8195-gce.h>
69         #address-cells = <2>;
70         #size-cells = <2>;
73             compatible = "mediatek,mt8195-disp-dsc";
74             reg = <0 0x1c009000 0 0x1000>;
76             power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
78             mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;