display/mediatek/mediatek%2Caal.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11   - Philipp Zabel <p.zabel@pengutronix.de>
24       - enum:
25           - mediatek,mt8173-disp-aal
26           - mediatek,mt8183-disp-aal
27           - mediatek,mt8195-mdp3-aal
28       - items:
29           - enum:
30               - mediatek,mt2712-disp-aal
31               - mediatek,mt6795-disp-aal
32           - const: mediatek,mt8173-disp-aal
33       - items:
34           - enum:
35               - mediatek,mt8186-disp-aal
36               - mediatek,mt8188-disp-aal
37               - mediatek,mt8192-disp-aal
38               - mediatek,mt8195-disp-aal
39               - mediatek,mt8365-disp-aal
40           - const: mediatek,mt8183-disp-aal
42   reg:
48   power-domains:
51       Documentation/devicetree/bindings/power/power-domain.yaml for details.
55       - description: AAL Clock
57   mediatek,gce-client-reg:
58     description: The register of client driver can be configured by gce with
59       4 arguments defined in this property, such as phandle of gce, subsys id,
60       register offset and size. Each GCE subsys id is mapping to a client
61       defined in the header include/dt-bindings/gce/<chip>-gce.h.
62     $ref: /schemas/types.yaml#/definitions/phandle-array
66   - compatible
67   - reg
68   - interrupts
69   - power-domains
70   - clocks
75   - |
76     #include <dt-bindings/interrupt-controller/arm-gic.h>
77     #include <dt-bindings/clock/mt8173-clk.h>
78     #include <dt-bindings/power/mt8173-power.h>
79     #include <dt-bindings/gce/mt8173-gce.h>
82         #address-cells = <2>;
83         #size-cells = <2>;
86            compatible = "mediatek,mt8173-disp-aal";
87            reg = <0 0x14015000 0 0x1000>;
89            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
91            mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;