bindings/display/allwinner%2Csun8i-a83t-dw-hdmi.yaml

1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A83t DWC HDMI TX Encoder
10   The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller
11   IP with Allwinner\'s own PHY IP. It supports audio and video outputs
14   These DT bindings follow the Synopsys DWC HDMI TX bindings defined
15   in bridge/synopsys,dw-hdmi.yaml with the following device-specific
19   - Chen-Yu Tsai <wens@csie.org>
20   - Maxime Ripard <mripard@kernel.org>
23   "#phy-cells":
28       - const: allwinner,sun8i-a83t-dw-hdmi
29       - const: allwinner,sun50i-h6-dw-hdmi
31       - items:
32           - enum:
33               - allwinner,sun8i-h3-dw-hdmi
34               - allwinner,sun8i-r40-dw-hdmi
35               - allwinner,sun50i-a64-dw-hdmi
36           - const: allwinner,sun8i-a83t-dw-hdmi
41   reg-io-width:
50       - description: Bus Clock
51       - description: Register Clock
52       - description: TMDS Clock
53       - description: HDMI CEC Clock
54       - description: HDCP Clock
55       - description: HDCP Bus Clock
57   clock-names:
60       - const: iahb
61       - const: isfr
62       - const: tmds
63       - const: cec
64       - const: hdcp
65       - const: hdcp-bus
70       - description: HDMI Controller Reset
71       - description: HDCP Reset
73   reset-names:
76       - const: ctrl
77       - const: hdcp
82       Phandle to the DWC HDMI PHY.
84   phy-names:
85     const: phy
87   hvcc-supply:
104           Output endpoints of the controller. Usually an HDMI
108       - port@0
109       - port@1
112   - compatible
113   - reg
114   - reg-io-width
115   - interrupts
116   - clocks
117   - clock-names
118   - resets
119   - reset-names
120   - phys
121   - phy-names
122   - ports
129           - allwinner,sun50i-h6-dw-hdmi
136     clock-names:
142     reset-names:
149   - |
150     #include <dt-bindings/interrupt-controller/arm-gic.h>
153      * This comes from the clock/sun8i-a83t-ccu.h and
154      * reset/sun8i-a83t-ccu.h headers, but we can't include them since
163     hdmi@1ee0000 {
164         compatible = "allwinner,sun8i-a83t-dw-hdmi";
166         reg-io-width = <1>;
170         clock-names = "iahb", "isfr", "tmds";
172         reset-names = "ctrl";
174         phy-names = "phy";
175         pinctrl-names = "default";
176         pinctrl-0 = <&hdmi_pins>;
179             #address-cells = <1>;
180             #size-cells = <0>;
186                     remote-endpoint = <&tcon1_out_hdmi>;
201   - |
202     #include <dt-bindings/interrupt-controller/arm-gic.h>
205      * This comes from the clock/sun50i-h6-ccu.h and
206      * reset/sun50i-h6-ccu.h headers, but we can't include them since
219     hdmi@6000000 {
220         compatible = "allwinner,sun50i-h6-dw-hdmi";
222         reg-io-width = <1>;
227         clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
228                       "hdcp-bus";
230         reset-names = "ctrl", "hdcp";
232         phy-names = "phy";
233         pinctrl-names = "default";
234         pinctrl-0 = <&hdmi_pins>;
237             #address-cells = <1>;
238             #size-cells = <0>;
244                     remote-endpoint = <&tcon_top_hdmi_out_hdmi>;