Lines Matching full:idle
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
7 title: Idle states
21 representing the range of dynamic idle states that a processor can enter at
23 parameters required to enter/exit specific idle states on a given processor.
26 2 - ARM idle states
40 PM implementation to put the processor in different idle states (which include
41 states listed above; "off" state is not an idle state since it does not have
44 Idle state parameters (e.g. entry latency) are platform specific and need to
48 The device tree binding definition for ARM idle states is the subject of this
52 3 - RISC-V idle states
56 suspend (or idle) states (ranging from simple WFI, power gating, etc). The
60 The platform specific suspend (or idle) states of a hart can be either
67 4 - idle-states definitions
70 Idle states are characterized for a specific system through a set of
72 triggered upon idle states entry and exit.
75 properties required to enter and exit an idle state:
77 ..__[EXEC]__|__[PREP]__|__[ENTRY]__|__[IDLE]__|__[EXIT]__|__[EXEC]__..
87 Diagram 1: CPU idle state execution phases
91 PREP: Preparation phase before committing the hardware to idle mode
98 ENTRY: The hardware is committed to idle mode. This period must run
99 to completion up to IDLE before anything else can happen.
101 IDLE: This is the actual energy-saving idle period. This may last
107 entry-latency: Worst case latency required to enter the idle state. The
111 idle state to be worthwhile energywise.
119 An idle CPU requires the expected min-residency time to select the most
120 appropriate idle state based on the expected expiry time of the next IRQ
125 of an idle state, e.g.:
140 idle state, and possibly to prevent that to guarantee reliable device
173 and denotes the energy costs incurred while entering and leaving the idle
176 shallower slope and essentially represents the energy consumption of the idle
179 min-residency is defined for a given idle state as the minimum expected
185 For sake of simplicity, let's consider a system with two idle states IDLE1,
211 Graph 2: idle states min-residency example
213 In graph 2 above, that takes into account idle states entry/exit energy
214 costs, it is clear that if the idle state residency time (i.e. time till next
215 wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state
222 idle state IDLE2 implies that after a suitable time, IDLE2 becomes more energy
226 shallower states in a system with multiple idle states) is defined
230 The definitions provided in this section underpin the idle states
234 5 - idle-states node
237 The processor idle states are defined within the idle-states node, which is
239 processor idle states, defined as device tree nodes, are listed.
241 On ARM systems, it is a container of processor idle states nodes. If the
243 just supports idle_standby, an idle-states node is not required.
249 Idle states have different enter/exit latency and residency values.
250 The idle states supported by the QCOM SoC are defined as -
262 hierarchy to enter standby states, when all cpus are idle. An interrupt brings
278 between the time it enters idle and the next known wake up. SPC mode is used
281 sequence for this idle state is programmed to power down the supply to the
329 const: idle-states
339 node[5] that is responsible for setting up CPU idle management in the OS
347 Each state node represents an idle state description and must be defined
350 The idle state entered by executing the wfi instruction (idle_standby
356 idle-states node. Please refer to the entry-method bindings
364 - qcom,idle-state-ret
365 - qcom,idle-state-spc
366 - qcom,idle-state-pc
367 - const: arm,idle-state
369 - arm,idle-state
370 - riscv,idle-state
378 (i.e. idle states node with entry-method property is set to "psci")
386 This property is required in idle state nodes of device tree meant
398 Worst case latency in microseconds required to enter the idle state.
402 Worst case latency in microseconds required to exit the idle state.
409 and entry, for this idle state to be considered worthwhile energy wise
425 idle-state-name:
428 A string used as a descriptive name for the idle state.
452 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
461 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
470 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
479 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
488 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
497 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
506 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
515 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
524 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
533 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
542 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
551 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
560 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
569 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
578 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
587 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
591 idle-states {
595 compatible = "arm,idle-state";
603 compatible = "arm,idle-state";
613 compatible = "arm,idle-state";
622 compatible = "arm,idle-state";
632 compatible = "arm,idle-state";
640 compatible = "arm,idle-state";
650 compatible = "arm,idle-state";
660 compatible = "arm,idle-state";
682 cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
689 cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
696 cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
703 cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
710 cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
717 cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
724 cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
731 cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
734 idle-states {
736 compatible = "arm,idle-state";
745 compatible = "arm,idle-state";
754 compatible = "arm,idle-state";
763 compatible = "arm,idle-state";
786 cpu-idle-states = <&CPU_RET_0_0>, <&CPU_NONRET_0_0>,
802 cpu-idle-states = <&CPU_RET_0_0>, <&CPU_NONRET_0_0>,
818 cpu-idle-states = <&CPU_RET_1_0>, <&CPU_NONRET_1_0>,
834 cpu-idle-states = <&CPU_RET_1_0>, <&CPU_NONRET_1_0>,
844 idle-states {
846 compatible = "riscv,idle-state";
854 compatible = "riscv,idle-state";
862 compatible = "riscv,idle-state";
872 compatible = "riscv,idle-state";
882 compatible = "riscv,idle-state";
890 compatible = "riscv,idle-state";
898 compatible = "riscv,idle-state";
908 compatible = "riscv,idle-state";
920 idle-states {
922 compatible = "qcom,idle-state-spc", "arm,idle-state";