bindings/cpu/cpu-capacity.txt

6 1 - Introduction
15 2 - CPU capacity definition
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
20 (e.g., ARM big.LITTLE systems) or maximum frequency at which CPUs can run
23 capture a first-order approximation of the relative performance of CPUs.
29 * A "single-threaded" or CPU affine benchmark
36 CPU capacities are obtained by running the Dhrystone benchmark on each CPU at
38 by the frequency (in MHz) at which the benchmark has been run, so that
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
54 available, final capacities are calculated by directly using capacity-dmips-
58 4 - Examples
61 Example 1 (ARM 64-bit, 6-cpu system, two clusters):
62 The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
64 is done by the operating system based on cluster0@max-freq=1100 and
65 cluster1@max-freq=850, final capacities are 1024 for cluster0 and
69 	#address-cells = <2>;
70 	#size-cells = <0>;
72 	cpu-map {
98 	idle-states {
99 		entry-method = "psci";
101 		CPU_SLEEP_0: cpu-sleep-0 {
102 			compatible = "arm,idle-state";
103 			arm,psci-suspend-param = <0x0010000>;
104 			local-timer-stop;
105 			entry-latency-us = <100>;
106 			exit-latency-us = <250>;
107 			min-residency-us = <150>;
110 		CLUSTER_SLEEP_0: cluster-sleep-0 {
111 			compatible = "arm,idle-state";
112 			arm,psci-suspend-param = <0x1010000>;
113 			local-timer-stop;
114 			entry-latency-us = <800>;
115 			exit-latency-us = <700>;
116 			min-residency-us = <2500>;
121 		compatible = "arm,cortex-a57";
124 		enable-method = "psci";
125 		next-level-cache = <&A57_L2>;
127 		cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
128 		capacity-dmips-mhz = <1024>;
132 		compatible = "arm,cortex-a57";
135 		enable-method = "psci";
136 		next-level-cache = <&A57_L2>;
138 		cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
139 		capacity-dmips-mhz = <1024>;
143 		compatible = "arm,cortex-a53";
146 		enable-method = "psci";
147 		next-level-cache = <&A53_L2>;
149 		cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
150 		capacity-dmips-mhz = <578>;
154 		compatible = "arm,cortex-a53";
157 		enable-method = "psci";
158 		next-level-cache = <&A53_L2>;
160 		cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
161 		capacity-dmips-mhz = <578>;
165 		compatible = "arm,cortex-a53";
168 		enable-method = "psci";
169 		next-level-cache = <&A53_L2>;
171 		cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
172 		capacity-dmips-mhz = <578>;
176 		compatible = "arm,cortex-a53";
179 		enable-method = "psci";
180 		next-level-cache = <&A53_L2>;
182 		cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
183 		capacity-dmips-mhz = <578>;
186 	A57_L2: l2-cache0 {
187 		compatible = "cache";
190 	A53_L2: l2-cache1 {
191 		compatible = "cache";
195 Example 2 (ARM 32-bit, 4-cpu system, two clusters,
197 capacities-dmips-mhz are scaled w.r.t. 2 (cpu@0 and cpu@1), this means that first
198 cpu@0 and cpu@1 are twice fast than cpu@2 and cpu@3 (at the same frequency)
201 	#address-cells = <1>;
202 	#size-cells = <0>;
206 		compatible = "arm,cortex-a15";
208 		capacity-dmips-mhz = <2>;
213 		compatible = "arm,cortex-a15";
215 		capacity-dmips-mhz = <2>;
220 		compatible = "arm,cortex-a15";
222 		capacity-dmips-mhz = <1>;
227 		compatible = "arm,cortex-a15";
229 		capacity-dmips-mhz = <1>;
234 5 - References
237 [1] ARM Linux Kernel documentation - CPUs bindings