bindings/clock/xlnx%2Cversal-clk.yaml

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Versal clock controller
10   - Michal Simek <michal.simek@amd.com>
13   The clock controller is a hardware block of Xilinx versal clock tree. It
20       - enum:
21           - xlnx,versal-clk
22           - xlnx,zynqmp-clk
23       - items:
24           - enum:
25               - xlnx,versal-net-clk
26           - const: xlnx,versal-clk
28   "#clock-cells":
35     maxItems: 8
37   clock-names:
39     maxItems: 8
42   - compatible
43   - "#clock-cells"
44   - clocks
45   - clock-names
50   - if:
55               - xlnx,versal-clk
61             - description: reference clock
62             - description: alternate reference clock for programmable logic
64         clock-names:
66             - const: ref
67             - const: pl_alt_ref
69   - if:
74               - xlnx,versal-net-clk
80             - description: reference clock
81             - description: alternate reference clock for programmable logic
82             - description: alternate reference clock
84         clock-names:
86             - const: ref
87             - const: pl_alt_ref
88             - const: alt_ref
90   - if:
95               - xlnx,zynqmp-clk
102             - description: PS reference clock
103             - description: reference clock for video system
104             - description: alternative PS reference clock
105             - description: auxiliary reference clock
106             - description: transceiver reference clock
107             - description: (E)MIO clock source  (Optional clock)
108             - description: GEM emio clock  (Optional clock)
109             - description: Watchdog external clock (Optional clock)
111         clock-names:
114             - const: pss_ref_clk
115             - const: video_clk
116             - const: pss_alt_ref_clk
117             - const: aux_ref_clk
118             - const: gt_crx_ref_clk
119             - pattern: "^mio_clk[00-77]+.*$"
120             - pattern: "gem[0-3]+_emio_clk.*$"
121             - pattern: "swdt[0-1]+_ext_clk.*$"
124   - |
126       zynqmp_firmware: zynqmp-firmware {
127         compatible = "xlnx,zynqmp-firmware";
129         versal_clk: clock-controller {
130           #clock-cells = <1>;
131           compatible = "xlnx,versal-clk";
133           clock-names = "ref", "pl_alt_ref";
138     clock-controller {
139         #clock-cells = <1>;
140         compatible = "xlnx,zynqmp-clk";
143         clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",