Lines Matching +full:control +full:- +full:parent
4 register-mapped multiplexer with multiple input clock signals or
6 gate or adjust the parent rate via a divider or multiplier.
15 register value selected parent clock
22 "index-starts-at-one" modified the scheme as follows:
24 register value selected clock parent
29 The binding must provide the register to control the mux. Optionally
30 the number of bits to shift the control field in the register can be
34 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
37 - compatible : shall be "ti,mux-clock" or "ti,composite-mux-clock".
38 - #clock-cells : from common clock binding; shall be set to 0.
39 - clocks : link phandles of parent clocks
40 - reg : register offset for register controlling adjustable mux
43 - clock-output-names : from common clock binding.
44 - ti,bit-shift : number of bits to shift the bit-mask, defaults to
46 - ti,index-starts-at-one : valid input select programming starts at 1, not
48 - ti,set-rate-parent : clk_set_rate is propagated to parent clock,
49 not supported by the composite-mux-clock subtype
50 - ti,latch-bit : latch the mux value to HW, only needed if the register
57 #clock-cells = <0>;
58 compatible = "ti,mux-clock";
61 ti,index-starts-at-one;
65 #clock-cells = <0>;
66 compatible = "ti,mux-clock";
68 ti,bit-shift = <24>;
73 #clock-cells = <0>;
74 compatible = "ti,composite-mux-clock";
76 ti,bit-shift = <4>;