ti/davinci/pll.txt

5 an multiplexers for various clock signals.
8 - compatible: shall be one of:
9 	- "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
10 	- "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
11 - reg: physical base address and size of the controller's register area.
12 - clocks: phandles corresponding to the clock names
13 - clock-names: names of the clock sources - depends on compatible string
14 	- for "ti,da850-pll0", shall be "clksrc", "extclksrc"
15 	- for "ti,da850-pll1", shall be "clksrc"
18 - ti,clkmode-square-wave: Indicates that the board is supplying a square
20 	This property is only valid when compatible = "ti,da850-pll0".
26 	Describes the main PLL clock output (before POSTDIV). The node name must
30 	- #clock-cells: shall be 0
33 	Describes the PLLDIVn divider clocks that provide the SYSCLKn clock
34 	domains. The node name must be "sysclk". Consumers of this node should
35 	use "n" in "SYSCLKn" as the index parameter for the clock cell.
38 	- #clock-cells: shall be 1
41 	Describes the AUXCLK output of the PLL. The node name must be "auxclk".
42 	This child node is only valid when compatible = "ti,da850-pll0".
45 	- #clock-cells: shall be 0
48 	Describes the OBSCLK output of the PLL. The node name must be "obsclk".
51 	- #clock-cells: shall be 0
56 	pll0: clock-controller@11000 {
57 		compatible = "ti,da850-pll0";
60 		clock-names = "clksrc", "extclksrc";
61 		ti,clkmode-square-wave;
64 			#clock-cells = <0>;
68 			#clock-cells = <1>;
72 			#clock-cells = <0>;
76 			#clock-cells = <0>;
80 	pll1: clock-controller@21a000 {
81 		compatible = "ti,da850-pll1";
84 		clock-names = "clksrc";
87 			#clock-cells = <1>;
91 			#clock-cells = <0>;
96 - Documentation/devicetree/bindings/clock/clock-bindings.txt