clock/ti/apll.txt

4 register-mapped APLL with usually two selectable input clocks
5 (reference clock and bypass clock), with analog phase locked
11 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
15 - compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
16 - #clock-cells : from common clock binding; shall be set to 0.
17 - clocks : link phandles of parent clocks (clk-ref and clk-bypass)
18 - reg : address and length of the register set for controlling the APLL.
20 	"control" - contains the control register offset
21 	"idlest" - contains the idlest register offset
22 	"autoidle" - contains the autoidle register offset (OMAP2 only)
23 - ti,clock-frequency : static clock frequency for the clock (OMAP2 only)
24 - ti,idlest-shift : bit-shift for the idlest field (OMAP2 only)
25 - ti,bit-shift : bit-shift for enable and autoidle fields (OMAP2 only)
29 		#clock-cells = <0>;
32 		compatible = "ti,dra7-apll-clock";
36 		#clock-cells = <0>;
37 		compatible = "ti,omap2-apll-clock";
39 		ti,bit-shift = <2>;
40 		ti,idlest-shift = <8>;
41 		ti,clock-frequency = <96000000>;