bindings/clock/starfive%2Cjh7110-voutcrg.yaml

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-voutcrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 Video-Output Clock and Reset Generator
10   - Xingyu Wu <xingyu.wu@starfivetech.com>
14     const: starfive,jh7110-voutcrg
21       - description: Vout Top core
22       - description: Vout Top Ahb
23       - description: Vout Top Axi
24       - description: Vout Top HDMI MCLK
25       - description: I2STX0 BCLK
26       - description: external HDMI pixel
28   clock-names:
30       - const: vout_src
31       - const: vout_top_ahb
32       - const: vout_top_axi
33       - const: vout_top_hdmitx0_mclk
34       - const: i2stx0_bclk
35       - const: hdmitx0_pixelclk
41   '#clock-cells':
44       See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
46   '#reset-cells':
49       See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
51   power-domains:
57   - compatible
58   - reg
59   - clocks
60   - clock-names
61   - resets
62   - '#clock-cells'
63   - '#reset-cells'
64   - power-domains
69   - |
70     #include <dt-bindings/clock/starfive,jh7110-crg.h>
71     #include <dt-bindings/power/starfive,jh7110-pmu.h>
72     #include <dt-bindings/reset/starfive,jh7110-crg.h>
74     voutcrg: clock-controller@295C0000 {
75         compatible = "starfive,jh7110-voutcrg";
83         clock-names = "vout_src", "vout_top_ahb",
87         #clock-cells = <1>;
88         #reset-cells = <1>;
89         power-domains = <&pwrc JH7110_PD_VOUT>;