Lines Matching +full:clock +full:- +full:indices
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
14 const: starfive,jh7110-ispcrg
21 - description: ISP Top core
22 - description: ISP Top Axi
23 - description: NOC ISP Bus
24 - description: external DVP
26 clock-names:
28 - const: isp_top_core
29 - const: isp_top_axi
30 - const: noc_bus_isp_axi
31 - const: dvp_clk
35 - description: ISP Top core
36 - description: ISP Top Axi
37 - description: NOC ISP Bus
39 '#clock-cells':
42 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
44 '#reset-cells':
47 See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
49 power-domains:
55 - compatible
56 - reg
57 - clocks
58 - clock-names
59 - resets
60 - '#clock-cells'
61 - '#reset-cells'
62 - power-domains
67 - |
68 #include <dt-bindings/clock/starfive,jh7110-crg.h>
69 #include <dt-bindings/power/starfive,jh7110-pmu.h>
70 #include <dt-bindings/reset/starfive,jh7110-crg.h>
72 ispcrg: clock-controller@19810000 {
73 compatible = "starfive,jh7110-ispcrg";
79 clock-names = "isp_top_core", "isp_top_axi",
84 #clock-cells = <1>;
85 #reset-cells = <1>;
86 power-domains = <&pwrc JH7110_PD_ISP>;