bindings/clock/st%2Cstm32-rcc.txt

4 The RCC IP is both a reset and a clock controller.
11   "st,stm32f42xx-rcc"
12   "st,stm32f469-rcc"
13   "st,stm32f746-rcc"
14   "st,stm32f769-rcc"
29 	rcc: rcc@40023800 {
32 		compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
42 The secondary index is the bit number within the RCC register bank, starting
43 from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).
49 drivers of the RCC IP, macros are available to generate the index in
53  - include/dt-bindings/mfd/stm32f4-rcc.h
59 		clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>
64 		clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>
117 		clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>
127 The index is the bit number within the RCC registers bank, starting from RCC
137 		resets	= <&rcc STM32F4_APB1_RESET(TIM2)>;