bindings/clock/sophgo%2Csg2042-clkgen.yaml

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/sophgo,sg2042-clkgen.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sophgo SG2042 Clock Generator for divider/mux/gate
10   - Chen Wang <unicorn_wang@outlook.com>
14     const: sophgo,sg2042-clkgen
21       - description: Main PLL
22       - description: Fixed PLL
23       - description: DDR PLL 0
24       - description: DDR PLL 1
26   clock-names:
28       - const: mpll
29       - const: fpll
30       - const: dpll0
31       - const: dpll1
33   '#clock-cells':
36       See <dt-bindings/clock/sophgo,sg2042-clkgen.h> for valid indices.
39   - compatible
40   - reg
41   - clocks
42   - clock-names
43   - '#clock-cells'
48   - |
49     clock-controller@30012000 {
50       compatible = "sophgo,sg2042-clkgen";
56       clock-names = "mpll",
60       #clock-cells = <1>;