bindings/clock/renesas%2Crzg2l-cpg.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode
10   - Geert Uytterhoeven <geert+renesas@glider.be>
13   On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module
15   similar, but does not have Clock Monitor Registers.
18     - The CPG block generates various core clocks,
19     - The Module Standby Mode block provides two functions:
20         1. Module Standby, providing a Clock Domain to control the clock supply
27       - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} and RZ/Five
28       - renesas,r9a07g044-cpg # RZ/G2{L,LC}
29       - renesas,r9a07g054-cpg # RZ/V2L
30       - renesas,r9a08g045-cpg # RZ/G3S
31       - renesas,r9a09g011-cpg # RZ/V2M
39   clock-names:
41       Clock source to CPG can be either from external clock input (EXCLK) or
45   '#clock-cells':
47       - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
48         and a core clock reference, as defined in
49         <dt-bindings/clock/r9a0*-cpg.h>,
50       - For module clocks, the two clock specifier cells must be "CPG_MOD" and
51         a module number, as defined in <dt-bindings/clock/r9a0*-cpg.h>.
54   '#power-domain-cells':
56       SoC devices that are part of the CPG/Module Standby Mode Clock Domain and
57       can be power-managed through Module Standby should refer to the CPG device
58       node in their "power-domains" property, as documented by the generic PM
59       Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
60       The power domain specifiers defined in <dt-bindings/clock/r9a0*-cpg.h> could
63   '#reset-cells':
66       <dt-bindings/clock/r9a0*-cpg.h>.
70   - compatible
71   - reg
72   - clocks
73   - clock-names
74   - '#clock-cells'
75   - '#power-domain-cells'
76   - '#reset-cells'
81   - if:
85             const: renesas,r9a08g045-cpg
88         '#power-domain-cells':
92         '#power-domain-cells':
96   - |
97     cpg: clock-controller@11010000 {
98             compatible = "renesas,r9a07g044-cpg";
101             clock-names = "extal";
102             #clock-cells = <2>;
103             #power-domain-cells = <0>;
104             #reset-cells = <1>;