bindings/clock/qcom%2Csm8450-dispcc.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller for SM8450
10   - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
14   domains on SM8450.
16   See also:: include/dt-bindings/clock/qcom,sm8450-dispcc.h
21       - qcom,sm8450-dispcc
26       - description: Board XO source
27       - description: Board Always On XO source
28       - description: Display's AHB clock
29       - description: sleep clock
30       - description: Byte clock from DSI PHY0
31       - description: Pixel clock from DSI PHY0
32       - description: Byte clock from DSI PHY1
33       - description: Pixel clock from DSI PHY1
34       - description: Link clock from DP PHY0
35       - description: VCO DIV clock from DP PHY0
36       - description: Link clock from DP PHY1
37       - description: VCO DIV clock from DP PHY1
38       - description: Link clock from DP PHY2
39       - description: VCO DIV clock from DP PHY2
40       - description: Link clock from DP PHY3
41       - description: VCO DIV clock from DP PHY3
43   power-domains:
48   required-opps:
54   - compatible
55   - clocks
56   - '#power-domain-cells'
59   - $ref: qcom,gcc.yaml#
64   - |
65     #include <dt-bindings/clock/qcom,gcc-sm8450.h>
66     #include <dt-bindings/clock/qcom,rpmh.h>
67     #include <dt-bindings/power/qcom,rpmhpd.h>
68     clock-controller@af00000 {
69       compatible = "qcom,sm8450-dispcc";
73                <&gcc GCC_DISP_AHB_CLK>,
79       #clock-cells = <1>;
80       #reset-cells = <1>;
81       #power-domain-cells = <1>;
82       power-domains = <&rpmhpd RPMHPD_MMCX>;
83       required-opps = <&rpmhpd_opp_low_svs>;